NXP FlexTimer Module is a configurable timer peripheral hence it should
be located under bindings/timer.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
These devices have an architecturally fixed 13 MHz clock device. But
thankfully you can put a default into a DTS binding so we don't have
to repeat it for all of them.
Signed-off-by: Andy Ross <andyross@google.com>
This commit adds the systick driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
A few bindings in the timer directory (for kernel timing sources) were
being used for counters (which can have alarms set, and have a distinct
API). Move these bindings to the counters directory.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
With this change, the LPTIM counter will be able to set
its timeout to the st,timeout value. So that system can
sleep for that period without interruption.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Timer driver using Microchip 32KHz based RTOS timer as the kernel
timer tick. The driver uses one of the 32-bit basic timers to
support the kernel's k_busy_wait API which is passed a wait
count in 1 us units. The 32-bit basic timer is selected by using
device tree chosen rtimer-busy-wait-timer set to the handle
of the desired 32-bit basic timer. If this driver is disabled,
the build system will select the ARM Cortex-M4 SysTick as the
kernel timer tick driver. The user should specify RTOS timer
as kernel tick by adding the compatible properity and setting
the status property to "okay" at the board or application level
device tree. The driver implements two internal API's for use
by the SoC PM. These two API's allow the SoC PM layer to disable
the timer used for k_busy_wait so the PLL can be disabled in
deep sleep. We used a custom API so we can disable this timer
in the deep sleep path when we know k_busy_wait will not be
called by other drivers or applications.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add timer instance in device tree
Add timer yaml file
Timer0/1/2/3 are common for MAX32xxx MCUs
MAX32655 has additional Timer4/5 which are low power timers
Co-authored-by: Mert Vatansever <mert.vatansever@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Relocate common properties from dedicated SOC's related
Cortex-M SysTick DTS files into the new generic
'cortex-m-systick.yaml' one.
Signed-off-by: Andrey VOLKOV <andrey.volkov@munic.io>
TI Dual-Mode timer is used as the arch timer for systick on J721E R5
cores. Add DM Timer for systick timer support.
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
The counter driver needs to know what is the maximum
counting frequency of each timer peripheral.
Let's add it to its DT.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add ability to set a wakeup counter in case OS Timer is
disabled in certain low power modes. Also add code to
compensate the tick value.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/timer, usb-c, usb and watchdog.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Change the name of the node for the lptim used as lowpower
tick source to stm32_lp_tick_source.
Once enabled, this node is known as stm32_lp_tick_source
That will avoid naming the node lptim1 or lptim2 or lptim, etc.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Revert "dts: bindings: LPtimer of stm32 has a x2 factor on its clock"
The stm32u5 lptim clock source has no prescaler to divide the
the LPTIM input clock frequency : no property required.
This reverts commit 572b286010.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use clock control API to retrieve the counter module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This change introduces a new PWM driver for all CC13/26xx SoC.
See the documentation in ti,cc13xx-cc26xx-timer-pwm.yaml for detailed
usage instructions.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
This commit addst support for the system timer peripheral which
can be found in Apollo4 SoCs.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This adds support for the TIMER1-4 counter.
Each counter has 24bits and can run on LP_CLK (15-32KHz)
or DIVN clock (32MHz) with prescaler 1-32.
Each counter can have one alarm set.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This is a new parameter to divide the LPTIM input clock
by a prescaler, changing the max reachable timeout of the LP timer.
It will divide the LPTIM input clock by 1 (reset value) up to 128.
The lptim configuration register is written with a 3bit value.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Modifying counter drivers (rtc and timer) to rely completely on
device tree and not on Kconfig of MDK flags.
Adapting dtsi for all SoCs and adapting test configuration.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Update machine timer drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on NIOSV devicetree.
Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
Align driver with changes introduced in the hal. `nrf_timer_frequency_set`
was changed to `nrf_timer_prescaler_set`, update driver accordingly.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add a st,static-prescaler optional property to DTS
of the stm32 where the LPTIM has a x2 factor on
its clock input.
This property is present or not depending on the stm32.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix all line-length errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(line-length)'
Using a limit is set to 100 columns, not touching the commandlines in
GitHub workflows (at least for now).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
We are about to add timer reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
NXP S32 System Timer module includes a 32-bit count-up timer and four
32-bit compare channels with a separate interrupt source for each
channel. The timer is driven by the module clock divided by an 8-bit
prescale value.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
DTS property attributes are (by default) not required.
Explicitly specifying `required: false` is redundant.
Perhaps a warning to that effect would be useful.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
various microchip bindings set 'girq-cells' and 'pcr-cells'
sections in the bindings. However the bindings where for the
client nodes and thus do not need to set these.
Signed-off-by: Kumar Gala <galak@kernel.org>
The CLINT (Core Local Interruptor) description was not aligned with
Linux. For example, there's no "riscv,clint0", but "sifive,clint0". The
peripheral is not described as an interrupt-controller either.
Ref. https://elixir.bootlin.com/linux/v5.18.14/source/arch/riscv/boot/
dts/starfive/jh7100.dtsi#L106
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
