2 commits

Author	SHA1	Message	Date
Yang Jialong	5a3f0b9506	arch: riscv64: smp: get msip base address from dts ... In most implements, the msip base address is 0x2000000. But the address is not fixed in all boards. Signed-off-by: Yang Jialong <yangjialong@vcore.com>	2024-11-27 06:58:57 -05:00
Filip Kokosinski	00b2ef8744	dts: set the riscv,isa property for virt-based targets ... This commit makes the devicetrees of the targets that are based on the QEMU `virt` machine more consistent with the rest of the RISC-V targets in Zephyr by: * adding the `riscv,isa` property * adding a compatible string which uniquely identifies the `virt` core Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>	2024-05-15 09:30:23 +02:00