Renamed andestech,plic-sw to andestech,mbox-plic-sw because the mbox node
is based on the PLIC interrupt controller node instead using the plic
hardware directly.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The plic-sw is the same hardware as the plic interrupt contoller and should
be used with intc_plic driver instead of separate mbox driver.
Renamed plic-sw node from "mbox: mbox-controller@e6400000" to
"plic_sw: interrupt-controller@e6400000".
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The ILPS22QS is an ultra-compact piezoresistive absolute pressure sensor
which functions as a digital output barometer, supporting dual full-scale
up to user- selectable 4060 hPa. The device delivers ultra-low pressure
noise with very low power consumption and operates over an extended
temperature range from -40 °C to +105 °C.
(https://www.st.com/en/mems-and-sensors/ilps22qs.html)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Rename the Silabs HCI driver to hci_silabs_efr32.c to better indicate what
hardware it supports. Also rename the associated devicetree binding and
Kconfig options to be consistent with the new driver name.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Add initial SoC support for the TI J721E SoC series Cortex-R5 core.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Some instances of the FLEXSPI IP permit limiting AHB bus access so that
no memory access requests will straddle a page boundary. Add a property
to manage this setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Updated ADXL345 driver with RTIO stream functionality.
Added Trigger intterupt functionality. RTIO stream is using
FIFO threshold.Together with RTIO stream, RTIO async read
is also implemented.
Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
Timer driver using Microchip 32KHz based RTOS timer as the kernel
timer tick. The driver uses one of the 32-bit basic timers to
support the kernel's k_busy_wait API which is passed a wait
count in 1 us units. The 32-bit basic timer is selected by using
device tree chosen rtimer-busy-wait-timer set to the handle
of the desired 32-bit basic timer. If this driver is disabled,
the build system will select the ARM Cortex-M4 SysTick as the
kernel timer tick driver. The user should specify RTOS timer
as kernel tick by adding the compatible properity and setting
the status property to "okay" at the board or application level
device tree. The driver implements two internal API's for use
by the SoC PM. These two API's allow the SoC PM layer to disable
the timer used for k_busy_wait so the PLL can be disabled in
deep sleep. We used a custom API so we can disable this timer
in the deep sleep path when we know k_busy_wait will not be
called by other drivers or applications.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Introduce bindings for Series 2 oscillators: HFRCODPLL, HFRCOEM23,
LFRCO and LFXO.
Add clock tree representation in devicetree `clocks` node.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Switch EFR32MG21 to use the device init HAL. This makes the init sequence
the same as the rest of Series 2.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The DC-DC converter was unconditionally initialized with default
settings on Series 2. Add device tree binding and nodes, and guard
call to init function. Map DT options to config header from HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add wsen_hids_2525020210002 driver with
the corrected name and compatibility with
the hal update as well as added new features.
Signed-off-by: Wajdi ELMuhtadi <wajdi.elmuhtadi@we-online.com>
Add support for Bosch bmp390 sensor, the drop in replacement for the
bmp388 with same register but different chip-id. This patch make use
of "bosch_bmp390" or "bosch_bmp388" and set the specific chip-id in a
data->chip-id variable, which then used to check against the register
value.
Additional, manual shift operation had been replaced with ENDIAN safe
macros and calibration values with target variable of int16_t add a
cast for it.
bmp388_spi: read register implementation wrong, fixed it.
tx-buffer must be <addr><dummy><dummy> in order to receive the
register value. Read registers in burst mode and have rx and tx
buffer same spi_buf to avoid clock stop and delay with nrf5.
Signed-off-by: Chris Ruehl <chris@gtsys.com.hk>
The NTC thermistor implementation assumes a constant pull-up voltage
and that the ADC channel is measured against a reference voltage so that
the absolute voltage across the NTC can be calculated. Based on the
relationship of `pullup-uv` and this absolute NTC voltage, the resistance
of the NTC is calculated.
There are applications where the "pullup-uv" is not constant, but VDD.
Most ADCs support relative measurements against VDD. If `pullup-uv` is not
defined, the implementation assumes now that the ADC channel is configured
to use VDD as a reference and therefore no millivolt conversion is
required.
Signed-off-by: Stefan Schwendeler <Stefan.Schwendeler@husqvarnagroup.com>
Added a new driver to support SPI communication via EUSART. Since the
Silabs EFR32MG24 family SoCs have only one USART, EUSART support is
necessary for implementing SPI functionality.
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
- boards: renesas: Add support for agt.
- drivers: counter: Add support for counter driver use agt
- dts: arm: Add support for agt.
- dts: bindings: Add support for agt counter driver.
- soc: renesas: Add support for agt counter driver.
- samples: drivers: counter: alarm: Add support for RA8
This is initial support with only basic functionality for counter
operation on Zephyr using AGT hardware, current support for
count source is limited to LOCO and PCLKB, other count source
like underflow signal external pin or AGTIO from another AGT
channel will be added in later support
Signed-off-by: Ha Nguyen <ha.nguyen.fz@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
support the configurations which apply for LVDS pads
+ termination resistor
+ current reference control
+ rx current boost
Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
The production version of the nRF54L15 SoC is now available, so remove
the initial Engineering A (EngA) preview version.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Some devices may belong to >1 power domain, so with the current design
this is something not possible to describe. It's worth to note that
Linux also uses the `power-domains` naming scheme, not `power-domain`.
This patch also introduces `power-domain-names` so that each entry in
`power-domains` can be given a name if needed. `#power-domain-cells`
is now required as well.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Enable the irqstr interrupt controller for the adsp-based
imx8mp.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Tested-by: Daniel Baluta <daniel.baluta@nxp.com>
Add 1-Wire register file
Some MAX32 MCUs has 1-Wire peripheral some one not
So that added in device related dtsi file.
Has 1-W Not have 1-W
MAX32655 MAX32662
MAX32666 MAX32670
MAX32680 MAX32672
MAX32690 MAX32675
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Initial support for SSD1322 OLED display driver. Only 1 bit color mode is
supported.
Most options map directly to values documented in the datasheet,
except segments-per-pixel, which I had to add to support the Newhaven
NHD-2.7-12864WDW3. This is a slightly odd feature, but in practice
it is a lot nicer to support it in the driver, and since we're currently
remapping pixels anyway, it makes sense to implement here.
This driver also has a configurable buffer size for the pixel conversion.
By using a larger buffer, we can potentially use DMA for the SPI transfer.
The default is set to 8, which is the smallest value that supports
segments-per-pixel = 2
Initial driver implementation by Lukasz Hawrylko <lukasz@hawrylko.pl>.
Additional options and configurability by Tobias Pisani <mail@topisani.dev>
Signed-off-by: Lukasz Hawrylko <lukasz@hawrylko.pl>
Signed-off-by: Tobias Pisani <mail@topisani.dev>
Co-authored-by: Lukasz Hawrylko <lukasz@hawrylko.pl>
Co-authored-by: Tobias Pisani <mail@topisani.dev>
Current nPM1300 charger driver does not work with batteries
without NTC thermistor. Added supported for this feature.
Signed-off-by: Javier Santos <jasr93@outlook.es>
This commit adds support for INA236 into the existing INA230 driver.
These two chips are similar enough to share most of the code.
The device can be defined the same way as INA230 and we only have
the extra option to select the high-precision mode.
```
ina236: ina236@40 {
status = "okay";
compatible = "ti,ina236", "ti,ina230";
reg = <0x40>;
adc-mode = "Bus and shunt voltage continuous";
vbus-conversion-time-us = <1100>;
vshunt-conversion-time-us = <1100>;
avg-count = <1>;
current-lsb-microamps = <1000>;
rshunt-micro-ohms = <15000>;
alert-gpios = <&gpiod 0 GPIO_ACTIVE_LOW>;
high-precision;
};
```
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
Enforce some minimum delay between enabling the voltage divider with a
GPIO and sampling the analog voltage. Without this delay the ADC can
easily sample the transient power up curve instead of the steady state
output.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Implement the parallel mode in the powertrain switch TLE9104.
This allows that OUT1 and OUT2 are controlled together, as well
as OUT3 and OUT4.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
It's more common (and more readable) convention to use lower-case
names for string-based device tree property values. Convert the HCI bus
and quirks to follow this convention. Also take advantage of the
recently added support for string-array enums to enforce that the
correct values are used.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Add I2C and SPI Device Tree nodes in SoC DTSI files to allow usage of these
peripherals.
Note that the SPI driver requires no modification to be functional on WB0.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
As per USB 2.0 specification 7.1.5.1: The voltage source on the pull-up
resistor must be derived from or controlled by the power supplied on the
USB cable such that when VBUS is removed, the pull-up resistor does not
supply current on the data line to which it is attached.
Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
Add a DTS binding file for Telit ME310G1 cellular modem based
on the binding for ME910G1 but without the mdm-reset-gpios as
the ME310 doesn't have a reset input.
Signed-off-by: Niklas Gürtler <niklas.guertler@e-obs.de>
Add a no-disconnect property that skips the call to disconnect the pin
during suspend, this is useful as not all gpio controllers supports pin
disconnection, and right now using the gpio-keys driver on one of those
results in a failed initialization if PM runtime is enabled.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Last 1k is used for saving VPR context and shall not be exposed.
Limiting RAM to 511k.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Split header files containing symbols denoting SAADC inputs
so that only supported inputs can be used for given device.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Add initial Feature Unit bindings allowing user to place the Feature
Unit inside UAC2 instance description. Currently the bindings facilitate
only specifying which controls are available on the Primary channel 0
and on each Logical channel. The number of Logical channels has to be
derived from data-source property.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Test the new c-macros for dt enums. The new macros are already used in
the existing macros. As an example, DT_ENUM_IDX(node_id, prop) uses
DT_ENUM_IDX_BY_IDX(node_id, prop, 0) to get its result. However, this is
insufficient for testing the complete functionality of these macros.
Therefore, additional tests are added to make sure they work
appropriately for other indices besides 0.
Signed-off-by: Joel Hirsbrunner <jhirsbrunner@baumer.com>
This concerns both `nordic,owned-memory` and `nordic,owned-partitions`.
Introduce a property named `nordic,access`, which is meant to replace
the `owner-id` and `perm-*` properties. It allows for describing how
multiple domains should access a single memory region, possibly with
different permissions per owner, but without having to create more than
one DT node for this purpose.
This change is also motivated by updated memory protection requirements
on the nRF54H20, which mandate that a given memory region must only be
reserved by one domain, even if multiple domains can have access to it.
This restriction is now described in the binding itself.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add SMARTDMA video driver. This driver uses the SMARTDMA engine as a
parallel camera interface, which can read QVGA frames from a camera
device. Due to SRAM constraints, the video driver divides the camera
stream into multiple horizontal video buffers as it streams them back to
an application.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The SMARTDMA is a programmable DMA engine, and supports custom firmware
in order to run complex DMA operations. Update the driver to increase
the flexibility users have when configuring the SMARTDMA with
custom firmware, and remove the RT500 display firmware specific
definitions and functionality from the driver.
This display setup is now handled from the MIPI DSI driver, since the
firmware used for this case is specific to the MIPI DSI IP.
This change also requires an update to the RT500 devicetree, as the
register definition for the SMARTDMA has changed, so the base address
must as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
TI tmp1075 driver implemented based on tmp108 driver.
The driver initializes the sensor based on the DTS.
Added tmp1075 example overlay file to thermometer sample.
All you need to do to use the sensor is to connect the I2C and
optionally interrupt line.
To see default DTS configuration option inspect `ti,tmp1075.yaml`
bindings file and sensor spec.
Signed-off-by: Paweł Czaplewski <pawel.czaplewski@arrow.com>
Reduce the valid scaling range for the gain multipliers and dividers to
provide more headroom on int64_t overflows in the calculations. Take
advantage of this headroom to perform all multiplications before
divisions.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Change the unit of the sense resistor in the devicetree binding from
micro-ohms to milli-ohms. This is done for three reasons.
Firstly, the maximum value resistor that can currently be represented
is 4.2 kOhms, due to the limitation of devicetree properties to 32 bits.
Secondly, storing the resistance at such a high resolution makes
overflows much more likely when the desired output unit is micro-amps,
not milli-amps.
Finally, micro-ohms, are an unnecessarily precise unit for the purpose
of these calculations, and a resolution that is not realistic to
achieve. The high resistor resolution results in large divisors that
reduce the resolution of outputs. Unlike resistors characterised down to
the micro-ohm, devices wanting to measure micro-amps are actually
realistic.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add common video interface binding. This binding contains the most
common properties needed to configure an endpoint subnode for data
exchange with other device.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
The stm32l4 devices were previously assigned the generic STM32 AES driver,
which turned out to be incompatible with the stm32l4 series. This commit
updates the nodes to use the new driver specifically designed for this
series.
Add missing node for stm32l4a6, stm32l4q5, stm32l4s5 and stm32l486 socs.
It appears stm32l4p5 and stm32l496 socs do not have the AES accelerator
present, so the nodes are removed from the dts files.
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
This patch completes the addition of support for the STM32L4 AES
accelerator by introducing conditional handling for different STM32 AES
HAL variants. Key changes include:
- Created device tree bindings `st,stm32l4-aes` for STM32L4 AES
- Replaced `copy_reverse_words` with `copy_words_adjust_endianness`
to handle endianness conversion for different variants.
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
NPCX9 and former chips defines two kinds of sub-power-states to support:
1. Standard wake-up time: if the chip needs to stay in the deep sleep
state more than 200 ms.
2. Instant wake-up time: if the chip needs to stay in the deep sleep
state less than 200 ms.
As NPCX4 can stay in the deep sleep state at more than 200 ms with the
instant wake-up capability, we can define only one sub-power state.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Update the devicetree binding for the nxp,kinetis-acmp comparator and
move the binding to dts/bindings/comparator.
The update to the binding includes:
- Remove unused io-channel-cells property
- Remove unused sensor-device include
- Adding missing properties dac config, discrete mode config, and
input configs.
- Rename properties to exclude redundant vendor prefix since props in
this binding are not inhereted, and as such, don't need to be
namespaced.
- Deprecate the old names of the renamed properties
The sensor based device driver has been updated to support both the
deprecated and new property names. This allows it to use both
nxp,enable-sample and filter-enable-sample for example.
Additionally, remove the unused io-channel-cells properties from
in-tree nodes of compatible = "nxp,kinetis-acmp"
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Adjust comparator nodes of nrf SoCs to exclude the unused
io-channel-cells property and simplify the comment describing how
to configure the comparator hardware block as COMP or LPCOMP for
SoCs which support this.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Counters configuration is missing in Devicetree for NXP MCX C series.
Add lptmr, rtc and pit configuration to Devicetree.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
If the `divider-int-0` or variations of these for each channel properties
are not specified, or if these is 0,
the driver dynamically configures the division ratio by specified cycles.
The driver will operate at the specified division ratio if a non-zero
value is specified for `divider-int-0`.
This is unchanged from previous behavior.
Please specify ``divider-int-0`` explicitly to make the same behavior as
before.
In addition, the default device tree properties related to the division
ratio have been removed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
NXP mcxc series has boot source configured to ROM. ROM bootloader
waits 5 sec for active peripheral detection timeout before jumping
to application in flash which makes booting very slow.
Change configuration to boot from flash and allow boot source
selection by external pin.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
IAP is a reference to the method of software interaction with the flash
used in the current driver implementing support for this flash. The
DT compatible should not be named like this.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a new `andestech,nceplic100` binding that inherits from the
`sifive,plic-1.0.0` binding. This is so that the Kconfig
`DT_HAS_ANDESTECH_NCEPLIC100_ENABLED` would be generated during
build.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
MAX14906 industrial 4 channel Input/Ouput GPIO expander with diagnostics.
Per channel diagnostics for open wire, over current.
Global diagnostic for power supply, communication and various fault
conditions.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Move the process of replacing numerical values with macros to
the header, and set the division ratio in a numeric without
using macros in the device tree.
Change `clk-div` defined in `renesas,ra-cgc-pclk.yaml` to `div`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
DeviceTree typically references the clock source using the `clocks`
property defined in `base.yaml`, so we'll change it to this.
Also delete the custom clock source definitions in
`renesas,ra-cgc-pclk-block.yaml`, `renesas,ra-cgc-pclk.yaml`, and
`renesas,ra-cgc-pll.yaml`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Changes the path name of a DTS node so that it can be used
as the stem of a BSP macro.
All nodes to be changed are referenced via labels,
so only the name is changed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Having the lowest possible interrupt priority is causing the
tests\arch\arm\arm_irq_zero_latency_levels test to fail.
This test reserves 2 priority levels for the low latency interrupts.
Since CYW20829 supports 3 interrupt bits, 6 becomes an invalid
value when 2 levels are reserved for the low latency interrupts.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Property "block-cycles" is required for node "zephyr,fstab,littlefs",
but source code did not get the value from dts file, now add it.
Additionally correct the wrong description of property "block-cycles"
in binding file.
Signed-off-by: Paul He <pawpawhe@gmail.com>
Update ADC bindings documentation to state that a domain clock is now
necessary if asynchronous clock is selected.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For STM32L1, U5 and WBA, the ADC always uses an asynchronous clock source,
so we add the default clock source in the clock node.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Some IBI TIR packets can be larger than the ibi data fifo size
which can prevent it from receiving the full packet. This adds
a data struct in to the driver data where data can be pushed
to as data is being transfered.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Enable support for 8 bit 8080 mode in the NXP LCDIC driver. Support
for programming the minimum duration of the write active/inactive signal
is also added, since this will be required to support high display
clocks in 8080 mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add mailbox node used for inter-process communication.
For DSP, we have a direct interrupt line to the core.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Change the STM32 Temperature Sensor bindings to accept the average slope
value in string form instead of integer. With this change, it is possible
to use the raw decimal value found in each MCU's datasheet instead of
needing to scale it (differently depending on series!). This also allows
regrouping the property in a single file to reduce duplication.
Also update all DTSI files affected by this change and the dietemp driver
to accept the property's new format.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Improve the STM32 dietemp sensor bindings by rewording the descriptions
of bindings and properties.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Reduce duplication in STM32 dietemp bindings by regrouping the 'ntc'
property declared in both "st,stm32-temp" and "st,stm32c0-temp-cal"
to the shared "st,stm32-temp-common" binding.
"st,stm32-temp-cal" is also modified to block 'ntc' property on include as
no dual-calibration sensors to date require it (this could be changed later
when need arises).
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Set the 'avgslope' property of 'st,stm32c0-temp-cal' to required, and
remove its default value, to ensure new series cannot be introduced without
setting the property to the correct value explicitly.
This change does not require any DTSI modification, because there are only
two files using this compatible (stm32f030.dtsi / stm32c0.dtsi), and both
of these already set 'avgslope' explicitly.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Set the 'avgslope' property of 'st,stm32-temp' to required, and remove its
default value, to ensure new series cannot be introduced without setting
the property to the correct value explicitly.
This change does not require any DTSI modification, because there are only
two files using this compatible (stm32f1.dtsi / stm32f2.dtsi), and both of
these already set 'avgslope' explicitly.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Set the 'v25' property of 'st,stm32-temp' to required, and remove its
default value, to ensure new series cannot be introduced without setting
the property to the correct value explicitly.
This change does not require any DTSI modification, because there are only
two files using this compatible (stm32f1.dtsi / stm32f2.dtsi), and both of
these already set 'v25' explicitly.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The typical value for V25 is different on the STM32F100 line compared
to other STM32F1 MCUs. Update the DTS property to the correct value.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add the missing 'avgslope' property to the DTSI for STM32F030/STM32F070.
This fixes improper results being returned by the driver: the correct
value for the average slope is 4.3mV/°C (4300 µV/°C), but the binding's
default value of 2.53mV/°C was used instead, since property was missing.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Remove the "Negative Temperature Coefficient" attribute from the STM32F2
die temperature sensor node, as it does not correspond to the hardware.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add virtual Cortex R8 SoC. This target does not represent a real SoC,
but can be easily run in Renode.
This will allow to easily test basic architecture support.
Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Add the <requires-ulbpr> property from the "jedec,spi-nor-common.yaml"
to the existing st,stm32-qspi-nor.yaml. So that external quad-NOR with
unlock the Global Block Protection (BPR) (opcode 0x98) is accepted.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
- Driver always initializes the device in the suspended state
- If CONFIG_PM_DEVICE_RUNTIME=n, device PM callback will be called with
RESUME action, thus setting up pins to default state and enabling the
peripheral
NOTE: when CONFIG_PM_DEVICE=n, the pinctrl sleep state will not be
available (-ENOENT) and so never applied, thus avoiding a pin
suspended->active transition.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add nodes for LPTMR. This is sufficient to enable their use as counter
devices when set to status okay.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add DT node and clocking of TPM peripherals, which are used for PWM.
Also change the soc clock enable code to not use preprocessor
conditionals.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add peripheral bridge definitions to DT, this also fixes the base
address of the GPIO peripherals which were faulting in the driver due to
the wrong reg address.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The Multi-Channel Inter-Processor Mailbox (MBOX) framework can be seen
as a more general version of the Inter-Processor Mailbox (IPM) framework.
An MBOX driver provides for multiple channels, where IPM provides for
only a single channel of communication.
Currently many applications are written to use IPM, while some are now
being written to use MBOX. This means if a platform wants to support both
types of apps a given it must have a driver for both frameworks. As MBOX
is the newer and more generic framework, new drivers are being added for
this framework only and older IPM drivers are being migrated to MBOX.
This leads to the situation where applications need to be written twice,
once for each framework, to run across all platforms.
The solution is to add a gasket driver that exposes the IPM interface
while using a MBOX driver in the back-end. This shim driver allows
platforms to only need an MBOX driver to support both types of
application. This IPM driver can be used when an application only
supports IPM but the platform only supports MBOX.
This will allow platforms and applications to be ported over to MBOX
independently of each other. Add this driver here.
Signed-off-by: Andrew Davis <afd@ti.com>
- Added `cs-supported` property to nrf-radio devicetree
- Added `HAS_HW_NRF_RADIO_CS` Kconfig option which is set if
`cs-supported` property is enabled
- Enabled `cs-supported` property for nrf54-series devices
- Disabled `cs-supported` on nrf54l15bsim because it is not
yet supported
Signed-off-by: Ivan Iushkov <ivan.iushkov@nordicsemi.no>
For nrf54h20 a range of combinations exist to configure the test and
debug domains data sources and sinks. Expose them in DTS to allow
configuring them. Also drop the previous style which was too rigid to
extend to cover all cases cleanly. The old style was only used in a
single sample application so far.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
This fixes the following warning:
> unit address and first address in 'reg' (0x80280000) don't match for
> /soc/sckcr@81280004
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Change the interrupt number of flash in device tree due to duplication
And disable CONFIG_FLASH as default
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Renamed soc from ace30_ptl to ace30.
We were previously using the wrong soc name.
The correct name is ace30.
There is only one ptl platform, but there can be several ace30 platforms.
Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
Add pwm yml file.
TIMER0/1/2/3 support pwm, LPTIMER0/1 not.
LPTIMER0/1 provide 16bits out that not meet pwm requirement.
Co-authored-by: Mert Vatansever <mert.vatansever@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Common uf2 partition configurations to avoid duplication in boards.
There appears to be a bit of confusion about exactly what a proper
UF2 partition map looks like for the nrf52840, so common dts
configurations should help to avoid confusion.
Configuration for SoftDevice v6 and v7 provided as thats what was
fouond in use in tree already.
Signed-off-by: Jacob Winther <jacob@9.nz>
Spi bus controller node names should follow recommended naming
convention from DT spec otherwise DTC will report a warning.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add property which indicates that UARTE support frame timeout
feature. Property is added to nrf54h20, nrf9280, nrf54l20 and
nrf54l15.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add support for VBUS measuring part of the TCPCI compliant device.
This device should be used as a child-node for the more specific
TCPC driver and referenced by the vbus property in the usb-c
connector node.
Signed-off-by: Michał Barnaś <barnas@google.com>
Introduce GPIO-based driver for MIPI DBI class that allows MIPI DBI
type A and B displays to be used on general platforms.
Since each data pin GPIO can be selected individually, the bus pins are
set in a loop, which has a significant negative impact on performance.
When using 8-bit mode and all the data GPIO pins are on the same port,
a look-up table is generated to set the whole port at once as a
performance optimization. This creates a ROM overhead of about 1 kiB.
Tested 8-bit 8080 mode with ILI9486 display on nRF52840-DK board.
Signed-off-by: Stefan Gloor <code@stefan-gloor.ch>
HFXO is represented as a child of the oscillators node. A new node is
created because it requires its own properties (see the binding for more
details).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
LFXO is represented as a child of the oscillators node. A new node is
created because it requires its own properties (see the binding for more
details).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- Create a new compatible: nordic,nrf53x-oscillators, as other series,
e.g. nRF54LX contain a similar but different IP (with PLL control,
etc.)
- Adjust DT: use recommended node name, remove redundant status okay.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Register all the lpi2c instances.
Add no-power-level property and update driver
to adapt no-power-level property.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This defines raspberrypi,pico-xosc along with a configurable startup
delay multiplier. On some boards, the XOSC takes longer to stabilize.
Signed-off-by: Xudong Zheng <7pkvm5aw@slicealias.com>
This fixes the following warning:
> unit address and first address in 'reg' (0x1002c0) don't match for
> /soc/dma@100200
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This fixes the following warning:
> unit address and first address in 'reg' (0x3fc70) don't match for
> /soc/peripheral@40000000/flash-controller@34000/flash@9fc70
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This fixes the following warnings:
> unit address and first address in 'reg' (0x40094000) don't match for
> /soc/peripheral@40000000/usbhs@144000
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This fixes the following warning:
> unit address and first address in 'reg' (0x3fc70) don't match for
> /soc/peripheral@40000000/flash-controller@34000/flash@9fc70
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This fixes the following warnings:
> unit address and first address in 'reg' (0x40094000) don't match for
> /soc/peripheral@40000000/usbhs@144000
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Now that we support internally connected channels we should make the
pinctrl configuration optional.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
Add MCO device nodes to the STM32 boards.
The set of supported boards are chosen to replace what is currently
supported in Kconfig.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add clock sources that can be output by the MCO on the stm32f1x and
stm32f10 connectivity line devices.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Add board support for eval board ganymed_bob, which
is a break-out-board for both soc variants.
Variants of the soc are GBM and GEN1.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Indicate in the STM32WB0 power controller binding that the SMPS output
current limitation is a feature only available on STM32WB05 and STM32WB09.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
`-` is preferred over `_` in devicetree property names.
Since, change `clk_src`, `clk_div`, and `clk_out_div` to
`clk-src`, `clk-div`, and `clk-out-div`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
There is an issue on the SHI hardware peripheral to detect CS
rising/failing with bits CSnFE/CSnRE in the EVSTAT2 register in
npcx9m7fb chip. This commit workarounds it by using MIWU to detect the
CS rising and failing.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The internal flash size of npcx9m7fb is 512KB. Reduce the default
Code RAM size from 320KB to 256KB because the Code RAM size is limited
by FLASH_SIZE/2 in the Chromebook EC application.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Add common default flash partition layout for nrf52840 as many boards
have used identical flash layouts.
The default flash layout was updated to remove scrach in 2022 (9a84258)
but almost all boards were still using the previous layout, so this
updates them to the new layout with allows for larger applications.
This commit also incorporates feeedback from @nordicjm in PR #77791 to
change slot0 to 0x00077000 and slot1 to 0x00075000: "If you use swap
using move, you need a sector for the data to be moved up by, and you
need space for the swap status fields, which is about a sector, so by
making the changes here you get the full 0x65000 for an image, without
these changes you get 0x64000.
Signed-off-by: Jacob Winther <jacob@9.nz>
Adds Device Tree include files for all MCUs in the STM32WB0 series.
These DTSI files only contain the supported peripherals for now.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add timer instance in device tree
Add timer yaml file
Timer0/1/2/3 are common for MAX32xxx MCUs
MAX32655 has additional Timer4/5 which are low power timers
Co-authored-by: Mert Vatansever <mert.vatansever@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Add information to the device tree if UARTE instance has a HW feature
which is the ENDTX_STOPTX short.
Add this property to all instances in nrf54hl15, nrf54l20, nrf9280
and nrf54h20.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
we have four i2C peripherals .
- three shared between stm32u031/73/83
- One between stm32u073/83
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
There are numbers of drivers for different PCA(L) series chip. They
share similiar register layout and control logic. This driver intends
to unify these drivers for PCA(L)xxxx series i2c gpio expanders.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Implement an option manual reset of the PCAL64XXA to allow the external
implementation of a retention of the port expander state.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Adds a new DTS prop for i3c devices as support for the CCC SETAASA
requires prior knowledge of the target if it supports it according
to i3c spec v1.1.1 section 5.19.3.23.
This will be used as an optimization for bus initialization.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Set a default value for constant-charge-voltage-max-microvolt, matching
the device hardware default, this ensure compatibility with existing
applications that did not specify the recently introduced property.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add general purpose partition tables to prevent
putting copied version of the same table into the
every ESP32 board dts.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add all the necessary files to add apds9253 Avago sensor driver.
Sensor available at https://docs.broadcom.com/doc/APDS-9253-001-DS
Signed-off-by: Margherita Milani <margherita.milani@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
This reverts commit 518de763a6.
This commit switched nrf5340 devices to use the icbmsg
IPC backend.
Unfortunately this backend is not currently supported
in the nrf5340bsim target (it is not properly configured)
which results in a segfault during its initialization.
As this issue is currently blocking CI for all BT development
in Zephyr, let's revert this provisionally while we add
support for it.
See
https://github.com/zephyrproject-rtos/zephyr/issues/78099
for more info.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add new binding and a node to nrf54h20. Update Kconfig and nrfx_config
to include nrfx_tbm driver when node with that compatible is enabled.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The current driver contains assembly code which is specific for the nRF51
SOC which makes it incompatible with other SOC's. This patch adds support
for other nRF SOC's as well. The timing is calucated based on the CPU clock
frequency, but can be configured manually as well if needed.
Changes have been verified on a Adafruit Feather nRF52840 Express board,
which contains a single NeoPixel RGB LED. Timings have been verified using
a scope connected to the WS1812 data line.
Signed-off-by: Chaim Zax <chaim.zax@zaxx.pro>
Added XGMAC0, XGMAC1, XGMAC2 device nodes in
intel_socfpga_agilex5 dts file with default
parameter values and default device node status
as 'disabled'.
Signed-off-by: Santosh Male <santosh.male@intel.com>
Devicetree binding for NXP mcxc oscillator is not available.
Add the binding to be able to configure the oscillator in devicetree.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Add configuration settings for the FOPT, FSEC, and flash configuration
offset to the FTFA module binding.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Charging a battery has three phases (compare Figure 8-2 in
https://www.ti.com/lit/ds/symlink/bq25180.pdf)
First is a pre-charge phase, then a constant current, then a constant
voltage phase.
During the pre-charge phase, the battery is only charged with a very low
current, to not damage the cells, because they are below a threshold,
that is considered healthy for the battery and need to be brought back
up to a healthy voltage.
Signed-off-by: Fabian Pflug <fabian.pflug@grandcentrix.net>
The linear battery charger will charge the connected battery up
to a specific voltage. This is different depending on the chemistry
of the battery. Most LiPo Batteries have a nominal voltage of 4.2V,
which is why the default voltage of the bq25180 is 4.2V.
Signed-off-by: Fabian Pflug <fabian.pflug@grandcentrix.net>
Add bindings for nrf-fll16m and nrf-lfclk and update in-tree nodes
and boards to use them in place of the fixed-clock binding.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The HFXO and LFXO oscillators have properties which need to be
specified in the devicetree. These properties are used by clock
controllers, which get these properties from the devicetree.
The BICR also contains these properties. For now, the properties
are duplicated in the bicr node in the devicetree.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add references to clock controllers so users can obtain
those for particular peripherals with DT macros like
DT_CLOCK_CTRL()
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
U-Blox LARA-R6 was added to modem_cellular, and an additional state
was introduced where the UART baudrate is changed if the modem supports
it
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
The STM32 SPI driver, `spi_ll_stm32.c`, reads the clock frequency via
`clock_control_get_rate()`. The first `clocks` index is used as subsystem
argument if there is no second index, but this is not the source clock for
SPI 1, 2, and 3.
This causes the prescaler value calculation to be incorrect, resulting in a
frequency potentially above the `spi-max-frequency` value.
Add clock source for SPI instances 1, 2 and 3, that matches the default
clock configuration register reset value, which resolves the issue.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
since stm32h7.dtsi is already include in st/h7/stm32h743.dtsi
we don't need to include here again.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The flash controller is nowadays supported on the M4 core.
Add the bank2-flash-size property to the board definitions as required
by the STM32 H7 flash driver.
Signed-off-by: Tomi Fontanilles <tomi.fontanilles@nordicsemi.no>
Add default memory partitioning for the nRF53 and nRF91 series devices.
As these partitions refer to TF-M and the TF-M layouts cannot be
modified, use the partitioning scheme from TF-M.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Adds support for settings/getting RTC time and using alarm/update feature.
The alarm option needs all fields to be set due to a hardware limitation.
RTC shares the same interrupt with the watchdog. Thus shared
interrupts must be enabled when WDT and RTC both need to trigger the ISR.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
add driver for Monolithic Power Systems MPM54304 with basic
functionality to enable/disable the buck regulators
Signed-off-by: Elias Speinle <e.speinle@vogl-electronic.com>
For almost all STM32 GPIO controllers, the number of supported GPIO
pins managed by a single controller is 16 (with some exceptions for
fewer). However, the default for ngpios in the device tree bindings
for gpio-controllers is 32; leading to inaccuracies in handling GPIO
for these controllers, such as presenting too many GPIOs in the GPIO
shell. This patch redefines the default for ngpios for "st,stm32-gpio"
compatible devices to 16 and adds the correct ngpios for the few
exceptions Zephyr current supports.
Signed-off-by: Michael R Rosen <mrrosen@alumni.cmu.edu>
The 'soft-off' state must be used when explicitly request by calling
`pm_state_force`. Set this state as disabled in dts ensures that the
pm policy manager will not use this state.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This commit moves the backup sram definition to the
series base dtsi file, the size is overwritten for socs
which have a bigger bkpsram.
The backup SRAM is available on all stm32h5 mcus.
stm32h503/523/533 have 2k
stm32h562/563/573 have 4k
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add the vref reference voltage in the DTS, so that the adc driver
can retrieve the value for conversion.
Signed-off-by: Marcin Wierzbicki <marcin.wierzbicki@accenture.com>
Add the yaml files needed for the dts binding of the Bosch bmp180 sensor.
V2 Fixup
--------
yaml fixup for complient checks
merge bmp180-i2c.yaml and bmp180.yaml
Signed-off-by: Chris Ruehl <chris@gtsys.com.hk>
Every High-Speed capable device must be able to enumerate at Full-Speed.
The functionality at different speeds can be different. Sometimes it is
possible to support exactly the same functionality on both High-Speed
and Full-Speed, but sometimes it is not. The problem is particurarly
relevant for UAC2 because it utilizes isochronous endpoints which means
that the available bandwidth is drastically different between High-Speed
and Full-Speed.
Full-Speed isochronous endpoint can support up to 1023 bytes per frame.
Typical 48 kHz 16-bit stereo stream consumes 48 * 2 * 2 = 192 bytes per
frame. Zephyr UAC2 instances with such streams are fine to work both at
Full-Speed and High-Speed.
An example stream that is too much for Full-Speed is the sometimes used
192 kHz 24-bit stereo (whether or not it is useful is out-of-scope here,
because it should be up to application developer) which would require
192 * 3 * 2 = 1152 bytes per frame.
Because the bandwidth required for audio stream depends on three
different parameters (sample rate, bit resolution and number of
channels), the UAC2 implementation should not automatically limit
available parameters to fit bandwidth requirements.
Adding explicit full-speed and high-speed boolean options to zephyr,uac2
compatible seems to be not only the easiest solution to the problem, but
also the most flexible one. Depending on the use case, the application
developer can then decide for example:
* to not support High-Speed at all - by having one zephyr,uac2 instance
with full-speed property
* to not support Full-Speed at all - by having one zephyr,uac2 instance
with high-speed property
* to support limited number of channels at Full-Speed and all channels
at High-Speed - by having one zephyr,uac2 instance with full-speed
property and separate instance with high-speed property
* to have exactly the same functionality at both speeds - by having one
zephyr,uac2 instance with both full-speed and high-speed properties
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Support additional properties from the linux `battery.yaml`.
The `ocv-capacity-table-0` definition differs from the Linux version as
we do not have a good way to generate variable length arrays in our
config structs, or a good way to separate out the percentage vs voltage
in the mapping.
We reduce the flexibility by enforcing a step size of 10%, which removes
the need for the percentage to be in the array and solves the variable
length problem.
To simplify the effort of defining these voltage curves, default curves
for a variety of chemistries have been added, extracted from datasheet
graphs of discharge curves from reputable manufacturers.
Signed-off-by: Jordan Yates <jordan@embeint.com>
I2S driver was merged after interrupt .dtsi was changed,
causing CI to fail. This updates it accordingly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Zephyr already has various FlexIO drivers but imxrt11xx didn't enable
the base flexio peripheral.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Some hardware configuration require rely on the ALERT/RDY
pin to know when and ADC conversion is completed.
The polling thread is left as fallback, when the pin
is not defined.
Signed-off-by: Efrain Calderon <efrain.calderon.estrada@gmail.com>
Enable DMIC clock in soc.c - attach to chip's audio PLL. Add pinmux
definitions for the DMIC peripheral. Add nodes to SoC's device tree for
the DMIC peripheral and its audio channels. Configure the DMIC
peripheral in board's device tree to enable audio capture.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Adds the use of generic touch reporting method for stmpe811 driver.
Signed-off-by: Dominik Lau <dlau@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Adds the use of generic touch reporting method for ft5336 driver.
Signed-off-by: Dominik Lau <dlau@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Adds common properties for touchscreen controllers.
Signed-off-by: Dominik Lau <dlau@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This transforms the existing driver for the Microchip MCP9808
to be used as a generic driver to be used with all
JEDEC JC 42.4 compliant temperature sensor chips.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The "channels-num" should not be used here, other system's parts are using
"channel-count" instead for the same purpose.
Also property's description has been сorrected.
Signed-off-by: Andrey VOLKOV <andrey.volkov@munic.io>
since h750 and h743 have the same irq wkup priority,
we can add wkup interrupt in h743.dsti and simply
include the file in h750.dtsi.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Allows MSTP register addresses to be changed in the device tree
to support different configuration SoCs.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Updated the counter_mcux_lptmr driver to support multiple
instances of the lptmr peripheral. Also added a new
binding property to identify if the user is using
counter-mode or pulse mode. since we were previously using the
prescaler value to check this which could be wrong
if used as a division value for getting the freq.
Added a property that allows the user to decide
what the counter value in lptmr should be divided by.
Cleaned up INIT macro for lptmr.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
dts: arm: nxp: mimxrt1180_evk: add GPT1/2 instance into devicetree
Enable GPT1/2 clock
Add GPT1/GPT2 instances
Set GPT2 as a counter, the default frequency is 240000000
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The driver in tree is for u-blox M8 devices, not M10. The M10 series
devices (from Protocol Version 23.01) use a different, non backwards
compatible interface for configuring the modem behaviour.
Of the two boards tested in the original PR, the "VMU RT1170" is
explicitly listed as having a u-blox NEO-M8N modem, while I have
been unable to find any information online about the "FMURT6" board.
Leaving the naming as-is will cause problems when M10 drivers are
contributed.
Signed-off-by: Jordan Yates <jordan@embeint.com>
This is just the driver for banks 0 to 3. Bank 4 will come via a
separate commit since it needs a different driver.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
This serves two main purposes:
- change the CPU clock via devicetree nodes
- provide the APB frequency to device drivers via the clock driver
interface
Theoretically this could also support choosing between the available
clock sources, but right now we only support LPOSC0 going into PLL0,
going into AHB.
Turning the PLL back off is also not supported since the only current
use case is to set the PLL frequency, turn it on, and switch the AHB
over to it.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
This is the bare minimum and includes the SoC, pinctrl, flash and
devicetree.
I had to include the flash driver that early because I couldn't make
Zephyr compile without flash driver nodes in the device tree.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
For applications that rely on low noise/variance in accelerometer
sample reading. Application can take advantage of integrated LPF
Thus this PR adds LPF configuration capability to the mc3419 driver
Signed-off-by: Anuj Pathak <anuj@croxel.com>
Since the clock node is not a child node of the soc node,
but from the root node.
This removes the warning log at compilation.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The lp5569 features a double functioning pin for enable and pwm control.
The chip, however, uses the first rising edge to initialize and get ready
for i2c communication, and then the pin alters function to pwm mode.
Add support for providing enable-gpios to the lp5569 in the dts, which
will make sure to assert the pin and wait for the chip to initialize
before attempting further configuration of the chip.
Signed-off-by: Emil Juhl <emdj@bang-olufsen.dk>
The lp5569 controller contains an internal charge pump which can be useful
for driving LEDs with a forward voltage greater than the lp5569 supply.
Taking advantage of the charge pump can alleviate the need for an external
boost converter.
Add a dts property, charge-pump-mode, to the ti,lp5569 binding with which
the cp_mode bits of the MISC register will be configured.
Following the datasheet, the possible configurations are:
0x00 -> disabled (default)
0x01 -> 1x mode
0x10 -> 1.5x mode
0x11 -> auto mode
Signed-off-by: Emil Juhl <emdj@bang-olufsen.dk>
Initial commit for entropy support on RA8
- drivers: entropy: implementation for TRNG driver of RA8x1
- dts: arm: add device node for trng of RA8x1
- boards: arm: enable support zephyr_entropy for ek_ra8m1 and
update board documentation
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Add definition of the nRF9280 SiP with its Application,
Radio, and Peripheral Processor (PPR) cores and a basic set
of peripherals: GRTC, GPIOs, GPIOTE, and UARTs and few others.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Co-authored-by: Andreas Moltumyr <andreas.moltumyr@nordicsemi.no>
The imx USDHC driver previously queried the peripheral's internal card
detect signal to check card presence if no card detect method was
configured. However, some boards do not route the card detect signal and
do not work correctly with the DAT3 detection method supported by this
peripheral. As a fallback, assume the card is present in the slot but
log a warning to the user.
Fixes#42227
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Updated the clocks that get initialized for the MCXN947
when using the LPTMR. The LPTMR allows the user to select
and Input clock, however said input clock must be
initialized before the user can select it.
Update description for clk-source in binding file.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
To prepare for supporting flexcan, can node should be
renamed to canxl to support both flexcan and canxl
Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
In SoC imxrt1010, edma channel has separate interrupt entry,
not like the rest of in-tree imxrt SoC series
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Adds "vib-overdrive-mv" device tree property to configure the overdrive
clamp at initialization.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Adds support for boot time configuration of the rated voltage at
initialization via "vib-rated-mv" devicetree property.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Adds the default value for the existing properties to the device tree
and fall back on those values at initialization if necessary.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
add reset control registers information (on RCC_BUS_RSTR LTDCRST bit)
for display peripheral reset.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add power management support for Apollo3/Apollo3P SPI, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add power management support for Apollo3/Apollo3P I2C, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add power management support for Apollo3/Apollo3P UART, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Add initial support for nuvoton npcm400, which is a chip
family of Satellite Management Controller(SMC).
Add ecst python scripts to append the header used by ROM Code
Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: James Chiang <cpchiang1@nuvoton.com>
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
Add lptmr support for ke17z, add related configuration for lptmr
driver.
Add supported CPU power states for idle, stop, partial stop 1, and
partial stop 2.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
This includes helper function for pin configuration
and a DT binding for the pinctrl DT node.
There's two important notes to be made regarding this
protocol:
* pinctrl drivers have no subsytem API to implement as opposed
to clock control drivers. Because of this (and the fact that
`pinctrl_configure_pins()` doesn't require a `struct device`
handle) the pinctrl driver consists only of a helper function,
which implements the `PINCTRL_CONFIGURE_PINS` command.
Additionally, the `scmi_protocol` structure is defined inside
the pinctrl helpers source file to avoid redundant code
(otherwise, each SCMI-based pinctrl driver would have to define
it its source file).
* each vendor may have their own set of pin propeties and DT
representations for them. Because of this, there can't be a
generic, SCMI-based pinctrl driver. As such, each vendor who
wants to use the SCMI support for pinctrl operations will have
to implement their pinctrl driver (which, to put it simply,
revolves around implemeting `pinctrl_configure_pins()`) and
make use of the pin configuration function introduced in this
commit. Moreover, this means that each vendor will have control
over the way their pin properties are encoded in the
`scmi_pinctrl_settings` structure.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This includes:
1) Source containing helper functions, each
implementing a command from the clock management
protocol.
2) A clock controller driver making use of said
helper functions and implementing the clock
subsystem API.
3) A DT binding for clock protocol node.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Introduce core support for ARM's SCMI (System Control and
Management Interface). This includes:
* shared memory (SHMEM) driver. This consists of a suite
of functions used to interact with the shared memory area.
* shared memory and doorbell-based transport layer driver.
Data is passed between platform and agent via shared
memory. Signaling is done using polling (PRE_KERNEL) and
doorbells (POST_KERNEL). This makes use of Zephyr MBOX API
(for signaling purposes) and the SHMEM driver (for polling
and data transfer).
* core driver - acts as glue between transport and protocol
layers. Provides synchronized access to transport layer
channels and channel assignment/initialization.
* infrastructure for creating SCMI protocols
This is based on ARM's SCMI Platform Design Document: DEN0056E.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.
Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
Change NuMaker M463/M467 series USBD clock source to HIRC48M.
This makes core-clock and its clock source PLL not required
to be multiple of 48MHz.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
- Initial support for RA6M2 SoC
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
First commit to support serial driver running on r_sci_uart for Renesas
RA devices.
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Background of this modification is to make gpio driver code
provided by Renesas vendor to be an official support for Renesas
MCU on Zephyr
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Update pinctrl driver which used for Renesas RA series with
PFS secure register
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Implements the driver for the OLED SSD1327 controller.
This driver is based on the ssd1306 driver due to their similarities.
Only the SPI control bus is supported.
Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
This commit add the description of the fmc in the SoC stm32l5, and the
description of the screen controller st7789v in the board stm32l562e-dk.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Add support of sys_poweroff API on m2l31x series.
It could support SPD0~2 standby or DPD0~1 deep power down mode.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
The offset of the peripheral is abstracted so that
the peripheral can be defined in RT118x.dtsi,that
is a common dtsi file for RT1180.
Due to cm33 core, add ns/s files which are served
on different status for cm33 core.
Add rt118x_cm7 dtsi file
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Now that the dts/bindings filter has been removed from
Devicetree Binding area, this area serves no real purpose.
Move the include/dt-bindings files to their respective areas.
Fix some of the orphaned dts/bindings paths.
Add regex filter for any binding with "zephyr" in the name to be
in the devicetree area.
Fix the imx_spc.h file being in it's own pm/ folder instead of
power/ like the other power related headers.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
accelerometer range is not suffixed with 'G' in the header
and also in the usages, but bindings use with suffix 'G'.
remove the suffix 'G' to have same reference.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Relocate common properties from dedicated SOC's related
Cortex-M SysTick DTS files into the new generic
'cortex-m-systick.yaml' one.
Signed-off-by: Andrey VOLKOV <andrey.volkov@munic.io>
Initial commit to suppor RA8D1 SoC
This is deveop base on RA8M1 so it will have similar stucture and
feature
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Add RTC driver support for NXP frdm_ke17z512, rtc doesn't exist on
frdm_ke17z board, delete rtc node from its dtsi file.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
Set LPO 1KHZ clock for RTC if clock source 'LPO' is selected.
The frdm_ke17z512 has no 32KHZ OSC, the RTC clock comes from SOSC,
RTC_CLKIN, LPO 1KHZ. But usually the SOSC is connected with 8MHZ
oscilator, so only 1kHZ LPO is usable.
Update the nxp,kinetis-rtc.yaml to select RTC clock source.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
Instead of forcing users to provide this setting, allow to describe
which signals require CLOCKPIN enablement at device nodes. This is later
captured by the pinctrl macros and applied in the pinctrl driver. Note
that name has been adjusted to nordic,clockpin-enable to avoid confusion
with clock related settings.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Enabled ENET ethernet port on Cortex-A Core for imx8mn EVK board.
Updated document for supported features.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Enabled ENET ethernet port on Cortex-A Core for imx8mm EVK board.
Updated suported featues in board document.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Device tree configuration for USB serial node and clock control
fix for proper device initialization.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Update i2c_emul.c to support i2c_target_register and i2c_target_unregister
function calls as well as support address forwarding in emulation.
Address forwarding helps us test IPCs in native sim. Instead of having to
emulate 2 separate cores, we can forward read/write requests from one bus
to another bus (effectively creating a loop). This way the same image can
simulate both the controller and the target.
Signed-off-by: Yuval Peress <peress@google.com>
This allows getting rid of the ngpios property, which is implicit in the
part number. It also prepares for configuring pins as open-drain on
supporting chips in the next commit.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
This chip is handled by the more generic mcp23xxx driver, which will get a
microchip,mcp23s17 compatible binding in the next commit.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Move the `overrun-character` property from the common Nordic SPI
binding to the `spi-controller` base binding. This gives users of the
SPI interface a way to query what the default value is at compile-time,
and potentially avoid allocation of large constant buffers.
Signed-off-by: Jordan Yates <jordan@embeint.com>
It's a superfluous value which used to be required by tooling, but now
we can remove it.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Between SoC revisions, the address was moved from 0x5F909000 in the
global domain, to 0xF0000000 in PPR's private address space.
Move the corresponding DT node out of `cpuppr_vpr` range to a separate
bus node, which is considered inaccessible to all cores but `cpuppr`.
This is expressed by selectively leaving out the `simple-bus` compatible
and `ranges` property, i.e., they're only set in `nrf54h20_cpuppr.dtsi`.
This lets the interrupt controller node remain visible at system level,
for the purpose of describing IRQ mappings between cores in devicetree.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
This change adds the device tree property for specifying oe-override
(output-enable override behavior), as well as defines for possible values
of the property.
RP2040 GPIOs can be configured to automatically invert the output-enable
signal from the selected peripheral function. This is useful for tasks like
writing efficient PIO code, such as in the i2c example in the rp2040
datasheet.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
On new SoCs, certain pins need to enable the clock setting on the pin
for it to work properly. For now, this has been handled internally in
the pinctrl driver, however, it appears to be an instance-specific
property (e.g. UARTE/SPIM instances in the fast domain do not require
such setting). Move the configuration of this settings to DT, the best
place where to have instance-specific hardware settings.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
HSFLL120 is a clock used by fast peripherals, and it is controlled by
the system controller. From an application perspective, it is a fixed
clock. Note that it has multiple outputs (clk_main @ 320MHz, and
clk_main2|4 which provide the main clock divided by 2 and 4,
respectivelu). Only the main frequency is represented for now.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Programming of the MLCS register was performed on the incorrect bits.
Additionally, saving the new version did not erase the previously set
value, which could result in an incorrect register value.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
nRF53X HV regulator differs from eg nRF52X as it offers a silent mode
option. For this reason, a new compatible is used, even if now such
capability is not exposed yet.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The SoC main supply is part of the POWER IP block. The POWER IP is a
kind of multi-purpose block, so each of its functions is described as a
child node in DT, like similar other MFD. This allows to have specific
properties, e.g. for DC/DC mode.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Some Nordic SoCs, like nRF52 contain an internal regulator for the main
SoC supply. Depending on the SoC, the regulator can have multiple
configurations (e.g. single/double stage), which mainly depends on
supporting "high-voltage" mode or not (VDDH pin supply). This patch adds
bindings for nRF5X regulator and nRF52X HV regulator.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The TMAG3001 is quite similar to the tmag5273 and can be used with just
some small modifications.
Signed-off-by: Fabian Pflug <fabian.pflug@grandcentrix.net>
Enable the Software Watchdog Timer instance on this board.
Now that SWT is enabled for this board and made the default watchdog,
sample.task_wdt.no_hw_fallback can be removed as is no longer needed.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert NXP SWT watchdog driver to a native driver and extend the
SWT supported functionalities and configuration options.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert power management to native drivers retaining existing
functionalities. Presently only SoC reset support and power control
initialization is supported, but these drivers will be extended to
support power management as well.
MC_ME and MC_RGM peripherals are common enough to be reused by other NXP
S32 devices, whereas PMC has specific implementations for each SoC
series.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
... so that a clear devicetree error is reported when the pinctrl-names
property is missing, not a quite cryptic compilation error about an
undeclared PINCTRL_STATE_*_UPPER_TOKEN symbol in pinctrl.h.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Necessary for supporting for EastRising 0.42 OLED display/board.
Some boards don't have external Iref set up. This is probably done in an
effort to save on component cost. This command is only documented in the
V1.1 revision of the SSD1306 datasheet.
See issue https://github.com/olikraus/u8g2/issues/1047
Signed-off-by: Théo Battrel <theo.battrel@nordicsemi.no>
This commit removes the requirement for pinctrl in the STM32 ADC binding.
This allows usage of ADC with internal channels only (no GPIO pin waste).
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
1. Support USB-C drivers TCPC, PPC, and VBUS with UTCPD H/W IP
2. UTCPD is interconnected with Timer-triggered EADC for updating
VBUS/VCONN voltage periodically
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Add support of sys_poweroff API on m46x series.
It could support SPD standby or DPD deep power down mode.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Rename it from litex,eth to litex,liteeth
to reflect the new name of the driver.
Zero got removed from the litex
ethernet compatible, as it now supports
multiple instances.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Convert pin control, GPIO and external interrupt controller drivers
based on SIUL2 peripheral to native drivers. This must be done in a
single commit to preserve atomicity, as these drivers depend on each
other.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add FPIO support for NXP frdm_ke17z and frdm_ke17z512,
the Fast GPIO(FGPIO) and GPIO share physical pins on the board.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
Adds device tree configs for dppic and ipct connections
between the Radio core and the Global domains.
The connections are required by the radio driver.
Signed-off-by: Piotr Koziar <piotr.koziar@nordicsemi.no>
Currently flash controller driver builds and runs only on M7.
This patch supports enablement of the driver on M4 CPUs. The
main issue in using the driver on M4 is that LL_GetFlashSize()
to read the flash size works only on M7 as the internal register
is not accessible from M4. So to use the driver on M4, add a dt
property, bank2-flash-size, to configure flash size of bank2.
this will allow gradual support of flash controller driver
on M4 of all supported STMH7 boards by defining the above
dt property and testing it. Currently this is verified only
on STM32H747i-disco board.
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
GR716A has two GRGPIO2 controllers.
This adds the GPIO controller description to the DTS and
makes the GPIO option available in the kernel configuration.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit adds a description for the lsm9ds1 sensor,
with a .h file containing all configuration options.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
This commit introduces the ability to set the CAN
interface from command-line. This is helpful
if we want to run multiple instances of the app
with different CAN interfaces without making
separate compilations for each instance.
Signed-off-by: Kacper Dalach <dalachowsky@gmail.com>
The driver right now only allows inverting the input value, which can be
useful for differential channels but is quite confusing for single ended
ones. Implement a simple output inversion flag instead to make up for
that.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Updates dts files to use the same GPIOTE interrupt lines as NRFX
for zephyr when TF-M is used.
Signed-off-by: Vidar Lillebø <vidar.lillebo@nordicsemi.no>
In S32K1 devices, Arm Systick clock frequency is equal to the
CPU core clock frequency, and its value can be obtained from
devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Correct license identifiers in two files copied from internal Nordic
repositories that were not properly adjusted for Zephyr:
- dts/bindings/flash_controller/nordic,rram-controller.yaml (added in
commit 3a8ee7df91)
- dts/bindings/misc/nordic,nrf-dppic-local.yaml (added in commit
796d09d2a6)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This patch adds support for the rx-invert and tx-invert device-tree
properties to the uart_lpc11u6x driver for USARTs 1, 2, 3 and 4.
Note that this feature is not supported by USART 0.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
remove litex,sys-clock-frequency from litex,clk,
because we already define that in the clock-frequency of cpu0.
This can be accessed via
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
These properties are not used by the driver at all, but are
inconveniently marked as required. Lets just remove them.
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
DTC warning caused by reg address not matching unit address,
but SRAM node address is translated by ranges property anyways.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The unit address didn't match reg which causes the warning, but
flexspi should be part of the peripheral node space anyways.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add new property 'nxp,reference-cells' for vref node.
Remove lpadc nodes 'nxp,reference-supply' property.
Add new property 'nxp,references' for lpadc nodes.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add specifier cells for nxp vref, when some other
peripherals use the vref to provide reference voltage,
this cells can be used to pass-in vref target voltage.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Remove d0i1 and change threshold for d0i2 to 10ms for pm setting
according to the requirements to pass CTS for chrome projects.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
According to the RV32M1 Series Manual, Rev 1.1 RV32M1 series supports the C
extension, and doesn't support the A extension. Apply fixes accordingly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
