Commit graph

7 commits

Author SHA1 Message Date
Marek Matej
d276cf753f soc: espressif: Extend the program header
Add new fields to the `esp_image_load_header_t`

* provide IROM and DROM fields to fix debugging features
* extend the header to up to 96 Bytes for future use

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-01-14 00:01:20 +01:00
Lucas Tamborrino
cdbd2b5558 soc: espressif: Add hardware initialization
Bring hardware initialization to zephyr code base.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-11-26 00:12:45 +01:00
Sylvio Alves
412921b594 soc: esp32c2: update linker files
Add new wifi sections into iram area.
Add new functions to iram area.
Remove unused entries.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-10-27 20:53:48 -05:00
Marcio Ribeiro
7e7672cb4b bugfix: esp32: allows QIO and QOUT flash modes
Allows QIO and QOUT flash mode to work on:
- esp32s2
- esp32s3
- esp32c2
- esp32c3
- esp32c6

Fixes #73677

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-10-16 12:26:52 +02:00
Marek Matej
bf2c67c441 soc: esp32c2: ESP WiFi heap
Provide symbols for the creation of dynamic memory pool.
Update the ROM-code SRAM usage according the IDF main.
Fix static allocations size check.
Increase iram_seg memory size for MCUboot.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-09-21 11:29:53 +02:00
Marcio Ribeiro
baf62b7a98 soc: esp32: XIP removed from Espressif targets
The way ESP32 XIP works (with MMU and cache) does no fit the way Zephyr XIP
is implemented, causing issues related to included Zephyr linker files.
Flash code still resides in flash for execution, but MMU/Cache handles it
in such way that XIP might not (or should not) be used with current Zephyr
approach. To address this problem, XIP configuration option is being
removed from Espressif targets.

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-31 06:47:52 -04:00
Raffael Rostagno
fad55d18ad soc: esp32c2: Add support to ESP32C2 and ESP8684
Files for SoC support: ESP32C2 and ESP8684 (same core).
Basic device tree configuration.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-16 14:08:22 -04:00