Remove hard-coded clock values from device tree nodes,
instead read the clock values from the clock controller
during run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Added XGMAC0, XGMAC1, XGMAC2 device nodes in
intel_socfpga_agilex5 dts file with default
parameter values and default device node status
as 'disabled'.
Signed-off-by: Santosh Male <santosh.male@intel.com>
add dts support for watchdog to accomodate watchdog driver bringup on
aglex and agilex5
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
adds dts support for general purpose timer to accomodate timer driver
bringup on aglex and agilex5
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Device tree for Intel SoCFPGA Agilex5 initial bring up. This is the
first version of device tree which enable four cores SMP and basic
drivers that needed by 'hello_world' and 'cli' applications.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This patch is to add Cadence QSPI NOR flash device tree element
for the Cadence QSPI NOR flash driver bringup
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
This patch is to increase kernel VM size to 1.5MB and
memory size to 2MB to ready for future driver bring up.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
This patch is to enhance the uart ns16550 driver to get clock frequency
from clock manager or devicetree if clock_frequency is defined.
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
This patch is to enable arm timer driver for Intel Agilex SoC FPGA.
The PPI's interrupt ID will be mapped into the interrupt ID
defined by SBSA in GIC-400 controller.
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
The armv8 timer, arm gic, and arm gic-v3-its don't use or need the
devicetree label property. Update the dts bindings to not require it and
remove setting of the label property in dts files.
Signed-off-by: Kumar Gala <galak@kernel.org>
