Commit graph

20 commits

Author SHA1 Message Date
Gerard Marull-Paretas
067f32731e modules: hal_gigadevice: use CONFIG_${ARCH} to select components
Instead of using custom SoC definitions. The selected components (e.g.
CMSIS), depend on the architecture selected by the SoC Kconfig options.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-10 15:05:54 +01:00
YuLong Yao
2086acfa0e soc: gd32a50x: introduce gd32a50x soc series
soc: gd32a50x: introduce gd32a50x soc series

Signed-off-by: YuLong Yao <feilongphone@gmail.com>
2023-01-12 21:45:38 +01:00
TOKITA Hiroshi
2e3cfec25d modules: Add option for enabling HAL debug functions
Add GD32_DBG_SUPPORT options to enable HAL debug functions.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-10-03 18:07:16 +02:00
TOKITA Hiroshi
db6d8c92ff modules: Add IRC configurations
Add options about Internal RC(IRC) oscillator.

- GD32_HAS_IRC_32K/40K indicates IRC types.
- GD32_LOW_SPEED_IRC_FREQUENCY is the numeric value of frequency

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-10-03 18:07:16 +02:00
Gerard Marull-Paretas
05b26df660 modules: hal_gigadevice: add support for CMP, TMU and SHRTIMER
The CMP, TMU and SHRTIMER modules were not compiled. Add them now that
GD32E50X series support is being added (this SoC has such units).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-12 14:13:49 +01:00
Gerard Marull-Paretas
184fb42957 modules: hal_gigadevice: add support for gd32e50x
Add some compile definitions necessary for the gd32e50x HAL and select
default crystal clock.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-12 14:13:49 +01:00
Gerard Marull-Paretas
4946a15f15 soc: arm: gigadevice: use common API headers
Stop relying on <soc.h> to access HAL APIs. Use generic, per-API headers
instead. Note that <soc.h> has been left as is for now, since ARM MPU
relies on a fragile chain of includes/type definitions.

This change should improve compilation efficiency, as we no longer pull
APIs that are not needed. A similar approach is followed by STM32
drivers.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-06-22 18:41:19 +09:00
YuLong Yao
1ad0b193d9 modules: arm: gigadevice: set HAXTL_VALUE for gd32_e103
set HAXTL_VALUE to GD32_HXTAL_8MHZ for gd32_e103.

Signed-off-by: YuLong Yao <feilongphone@gmail.com>
2022-03-01 18:06:14 +01:00
TOKITA Hiroshi
5c7a0ef888 drivers: interrupt-controller: add Nuclei ECLIC driver
Add support for the ECLIC interrupt controller
which is used with the Nuclei processor core.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
TOKITA Hiroshi
5f3a6af91c modules: Add Configurations for GD32VF103
Add configuration for GD32VF103 SoC.

- Add compiler definition HXTAL_VALUE for compile GigaDevice's HAL.
- Redefine gd32_cmsis_dir for source commonize.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
HaiLong Yang
33a44a7748 modules: hal_gigadevie: add CEC and TSI drivers
Add CEC and TSI drivers from GD32F3X0.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
2021-12-13 20:27:30 -05:00
Gerard Marull-Paretas
f8017dc5ad drivers: pinctrl: gd32: initial support for AFIO based SoCs
Add a pin control driver for GD32 SoCs using the AFIO model.

Thanks to Gerson Fernando Budke for testing and implementation
suggestions.

Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
543a3843ff drivers: pinctrl: gd32: initial support for AF based SoCs
Add a pin control driver for GD32 SoCs using the AF model.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
df6dd42ca3 modules: hal_gigadevice: include module headers
Include the module `include` folder to allow access to the dt-bindings
helpers.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerson Fernando Budke
7fba91f383 modules: hal_gigadevice: Set directories to lowercase
This rework module hal_gigadevice to be compliance with rule
that requires firmware libraries directories names be lowercase.
This rule was created at hal_gigadevice/README and it is not
a Zephyr general rule. This only affect how hal_gigadevice is
used.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-11-20 11:54:08 -05:00
Gerard Marull-Paretas
5f99dc7a1c modules: hal_gigadevice: add missing drivers
Add missing drivers included in F4XX HAL:

- DCI
- IPA
- IREF
- SYSCFG
- TLI
- TRNG

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
74538a1709 modules: hal_gigadevice: make compile definitions global
GD32F4XX requires access to SoC definitions (e.g. GD32F450) when
including library header files, so expose them at Zephyr level.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
20d3711984 modules: hal_gigadevice: adjust CMake
Adjust CMake according to latest SoC changes.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerson Fernando Budke
087be00b58 soc: arm: Introduce gigadevice soc
Add gigadevice soc initial version.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-10-28 11:17:25 +02:00
Gerson Fernando Budke
6d8c03422c modules: Add gigadevice hal module
This add access to modules/hal/gigadevice with three firmware
libraries by updating west.yaml file:

 - GD32E10X ARM (Cortex-M4F)
 - GD32F403 ARM (Cortex-M4F)
 - GD32VF103 RISC-V (Nucleisys Bumblebee core)

It introduce module/hal_gigadevice, which contains all Cmake
and Kconfig rules to build GigaDevice SoCs into zephyr main
tree.

Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2021-10-28 11:17:25 +02:00