Add a testcase for the stm32F412 or stm32F413
configuring the SDIO clock at 48MHz from the PLLI2S
Tested on the stm32f413h disco kit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Convert them to native YAML lists. Support for space-separated
lists was deprecated in Twister a long time ago.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Tests the ADC clock domain on the stm32g0 serie
Possible ADC clock sources are SYStem clock (default) or PLL_P.
No clock source HSI for the ADC tested here.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Disable the pll2 when clearing the clock config prior to
testing the clock_control driver for the stm32h7
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add support for enabling the clock security system, which can detect
failures of the HSE clock.
Includes tests for nucleo_h743zi and nucleo_g474re.
Signed-off-by: Kevin ORourke <kevin.orourke@ferroamp.se>
Added a test case that generates a 160 MHz system clock
using a 16777216 Hz HSE clock and also using a 16 MHz HSI
Signed-off-by: Jatty Andriean <jandriea@outlook.com>
Adapt the clock scheme for testing the clock on the stm32h573i_dk.
By default the HSI is 32MHz (div-by-2).
Only scheme for pll sourced by HSI is useful at max freq of 240MHz.
Configure the usart1-console clock to be csi to always get
a valid clock source in any usecase.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Twister now supports using YAML lists for all fields that were written
as space-separated lists. Used twister_to_list.py script. Some artifacts
on string length are due to how ruamel dumps content.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add clock_control_get_status checks to the stm32_common_devices adc
and i2c tests, to verify that checking the status of gating clocks and
domain clock sources works.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Split STM32 device clock configuration file so that each driver has its
own tests in its own file
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a test for testing STM32 I2S domain clock on STM32F401 board.
Add an ifdef on I2C test as F4 does not have a domain clock for I2C.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This makes sure clock selection works even if the registers aren't in their
default (reset) state.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Adds the configurations for testing the clock controller driver
of the stm32H5 serie coreon stm32h573i disco kit
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix all line-length errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(line-length)'
Using a limit is set to 100 columns, not touching the commandlines in
GitHub workflows (at least for now).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change the name of the STM32_CLOCK_BUS_APB2 RCC resgister
of the stm32g0 to STM32_CLOCK_BUS_APB1_2
in the testcase for the stm32g0 device.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
integration_platforms help us control what get built/executed in CI and
for each PR submitted. They do not filter out platforms, instead they
just minimize the amount of builds/testing for a particular
tests/sample.
Tests still run on all supported platforms when not in integration mode.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When it needs to access perck clock speed, clock_control driver is using
LL API to read RCC registers and compute frequency.
We're using the exact same method to test the frequency and as a result
we were not able to detect that there was an issue when configuring this
clock.
Add a specific case to this test in order to verify perck domain clock if
perck is used in SPI clk configuration.
We're now able to detect issues (and test is failing).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Perform some rework in messages displayed in case of failure to ease
readability:
- remove redundant information
- add missing information
- convert registers values to hex
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Test was using "clock-names" property to query domain clock configuration.
This is not working since clock-names was removed in the last step of the
feature implementation and whole macro was always reporting DT_NO_CLOCK.
This issue went undetected because of an additional issue in the exception
case which was testing "zassert_true(1, .." instead of "zassert_true(0, .".
Fix both issues to make the test efficient again.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
test cases in
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices
are move to new ztest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
test cases in
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core
are moved to new ztest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
test cases in
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices
are moved to new ztest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
test cases in
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core
are moved to new zest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
test cases in
tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices
are moved to new ztest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
test cases in
tests/dirvers/clock_control/stm32_clock_configuration/stm32_common_core
are moved to new ztest API
Signed-off-by: Meng xianglin <xianglinx.meng@intel.com>
On some tests adc node is enabled w/o setting any domain clock.
This is made on purpose but deserves a comment to avoid surprises
for the reader.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In the continuation of the previous commit, replace _OPT_ by _DOMAIN_
in macros relating to this feature.
hen, adapt drivers and tests to this new wording.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a bunch of missing "zephyr/" prefixes to #include statements in
various test and test framework files.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
In tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices
test suite, core_init.overlay configure msis to use pll-mode.
Since pll-mode is not configured for msik in spi1_msik variant the test
fails since both clocks should support the same configuration regarding
pll mode (an assert in raised in the driver).
Fix this in spi1_msik test variant.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds a test case that configures an alternative clock source
for an ADC peripheral.
In case no alt clock is available, only the gating clock is enabled
and disabled.
Unlike the i2c and lptim test, the actual gating clock frequency is
not checked, because for the adc there seems to be no uniform way
to retrieve the frequency via the hal.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
For the STM32G0, STM32G4, and STM32WL enable the adc node in one
configuration, and select the PLL_P output as its clock source.
PLL_P divider is chosen to be 20 to make sure it's a unique frequency.
- g0, and g4 have pll as sysclk
- wl has hse as sysclock
The test configurations and the overlay-files are renamed accordingly.
All overlays that don't specify an alternative clock source still
make sure that the adc node is "okay" to be able to perform basic test.
The basic test only turns on and off the gate clock without checking the
frequency.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The test checks if the peripheral gating clock was correctly disabled
after the test, but accidentally the I2C_CLK was checked instead of the
LPTIM_CLK.
This commit fixes this by using __HAL_RCC_LPTIM1_IS_CLK_ENABLED instead.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The nucleo_wl55jc according to the datasheet does have a
NT2016SF-32M-END5875A 32MHz TCXO as HSE, therefore needs
enable the "hse-tcxo;" property to work, this was not the case
for the clock_configuration/stm32_common_devices test cases.
Additionally, remove the comment about about ST-Link clock,
because the source is the tcxo and not the ST-Link.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
STM32_DT_CLOCKS was designed to take a device tree node label name as
argument: STM32_DT_CLOCKS(uart1)
Change its implementation to take a node identifier instead:
STM32_DT_CLOCKS(DT_NODELABEL(uart1)).
This make its usage more flexible since the argument can now be extracted
from other DT macros such as DT_PARENT. Then, the following can be done:
STM32_DT_CLOCKS(DT_PARENT(child_node_label)).
Since it is now possible implement STM32_DT_INST_CLOCKS using
STM32_DT_CLOCKS.
Finally, update existing STM32_DT_CLOCKS users and convert
STM32_INST_CLOCK_INFO users to STM32_CLOCK_INFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
