The variable config in sw_port_off() is not used, and it's
causing CI build error about unused variable. So remove it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch changes GPIO initialization
to be in PORT_OFF state by default.
Also, if no transceiver is attached to the signals,
the GPIOs are configured to be disconnected to preserve power.
I tested this on a prototype board where we are going to have
a debugger in a low-power context.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Since CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is tied to the slow RTC clock
for the nRF53, use the default SYSCLK of 64MHz instead.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Hardcode the lookup table for SWDP requests.
This is an optimization to save some space.
Documentation was added to understand the values.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Add API to read count bits from SWDIO into data LSB first.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Move low-level GPIO functions to a separate file and use GPIO driver
API if low-level GPIO support is not available for the platform.
Allows alternative pin configuration using only two pins, clk and dio.
Improve binding description.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add Serial Wire Debug Port interface driver API and bit-bang driver.
The driver requires a simple Hardware Interface Circuits (HICs),
where signals CLK, DOUT, DIN, ENn, OE_ENn, RESETn
are connected to board GPIOs and buffered signals SWD_CLK and SWD_DIO
to the target.
Signal OE_ENn controls the direction of the Serial Wire (SWD_DIO),
ENn the buffers SWD_CLK possibly others and enables/disables HIC.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
