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circuitpyt
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602 changed files with 5672 additions and 11489 deletions
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@ -4168,8 +4168,6 @@ TI K3 Platforms:
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- dnltz
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files:
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- boards/ti/*am62*/
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- drivers/*/*davinci*
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- drivers/*/*omap*
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- drivers/*/*ti_k3*
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- dts/bindings/*/ti,k3*
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- soc/ti/k3/
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@ -8,7 +8,6 @@ if CPU_HAS_MPU
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config ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
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int
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default 256 if ARM_MPU && ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE
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default 128 if ARM_MPU && FPU_SHARING && MPU_STACK_GUARD
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default 64 if ARM_MPU && AARCH32_ARMV8_R
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default 32 if ARM_MPU
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default 4
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@ -143,6 +143,17 @@ config ARM64_SAFE_EXCEPTION_STACK
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used for user stack overflow checking, because kernel stack support
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the checking work.
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config ARM64_ENABLE_FRAME_POINTER
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bool
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depends on OVERRIDE_FRAME_POINTER_DEFAULT && !OMIT_FRAME_POINTER
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depends on !FRAME_POINTER
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select DEPRECATED
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help
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Deprecated. Use CONFIG_FRAME_POINTER instead.
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Hidden option to simplify access to OVERRIDE_FRAME_POINTER_DEFAULT
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and OMIT_FRAME_POINTER. It is automatically enabled when the frame
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pointer unwinding is enabled.
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config ARM64_EXCEPTION_STACK_TRACE
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bool
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default y
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@ -27,6 +27,8 @@ zephyr_library_sources_ifdef(
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multilevel_irq.c
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)
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zephyr_library_sources_ifdef(CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION multilevel_irq_legacy.c)
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zephyr_library_sources_ifdef(CONFIG_SHARED_INTERRUPTS shared_irq.c)
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if(NOT CONFIG_ARCH_HAS_TIMING_FUNCTIONS AND
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@ -16,6 +16,21 @@ config SEMIHOST
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This option is compatible with hardware and with QEMU, through the
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(automatic) use of the -semihosting-config switch when invoking it.
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config LEGACY_MULTI_LEVEL_TABLE_GENERATION
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bool "Auto generates the multi-level interrupt LUT (deprecated)"
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default y
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select DEPRECATED
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depends on MULTI_LEVEL_INTERRUPTS
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depends on !PLIC
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depends on !NXP_IRQSTEER
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depends on !RV32M1_INTMUX
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depends on !CAVS_ICTL
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depends on !DW_ICTL_ACE
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depends on !DW_ICTL
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help
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A make-shift Kconfig to continue generating the multi-level interrupt LUT
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with the legacy way using DT macros.
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config ISR_TABLE_SHELL
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bool "Shell command to dump the ISR tables"
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depends on GEN_SW_ISR_TABLE
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72
arch/common/multilevel_irq_legacy.c
Normal file
72
arch/common/multilevel_irq_legacy.c
Normal file
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@ -0,0 +1,72 @@
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/*
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* Copyright (c) 2018 Intel Corporation.
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* Copyright (c) 2024 Meta.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/sys/util.h>
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/**
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* @file
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* @brief This file houses the deprecated legacy macros-generated multi-level interrupt lookup
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* table code, compiled when `CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is enabled.
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*/
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/*
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* Insert code if the node_id is an interrupt controller
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*/
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#define Z_IF_DT_IS_INTC(node_id, code) \
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IF_ENABLED(DT_NODE_HAS_PROP(node_id, interrupt_controller), (code))
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/*
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* Expands to node_id if its IRQN is equal to `_irq`, nothing otherwise
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* This only works for `_irq` between 0 & 4095, see `IS_EQ`
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*/
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#define Z_IF_DT_INTC_IRQN_EQ(node_id, _irq) IF_ENABLED(IS_EQ(DT_IRQ(node_id, irq), _irq), (node_id))
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/*
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* Expands to node_id if it's an interrupt controller & its IRQN is `irq`, or nothing otherwise
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*/
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#define Z_DT_INTC_GET_IRQN(node_id, _irq) \
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Z_IF_DT_IS_INTC(node_id, Z_IF_DT_INTC_IRQN_EQ(node_id, _irq))
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/**
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* Loop through child of "/soc" and get root interrupt controllers with `_irq` as IRQN,
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* this assumes only one device has the IRQN
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* @param _irq irq number
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* @return node_id(s) that has the `_irq` number, or empty if none of them has the `_irq`
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*/
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#define INTC_DT_IRQN_GET(_irq) \
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DT_FOREACH_CHILD_STATUS_OKAY_VARGS(DT_PATH(soc), Z_DT_INTC_GET_IRQN, _irq)
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#define INIT_IRQ_PARENT_OFFSET_2ND(n, d, i, o) \
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IRQ_PARENT_ENTRY_DEFINE(intc_l2_##n, DEVICE_DT_GET_OR_NULL(d), i, o, 2)
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#define IRQ_INDEX_TO_OFFSET(i, base) (base + i * CONFIG_MAX_IRQ_PER_AGGREGATOR)
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#define CAT_2ND_LVL_LIST(i, base) \
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INIT_IRQ_PARENT_OFFSET_2ND(i, INTC_DT_IRQN_GET(CONFIG_2ND_LVL_INTR_0##i##_OFFSET), \
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CONFIG_2ND_LVL_INTR_0##i##_OFFSET, \
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IRQ_INDEX_TO_OFFSET(i, base))
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LISTIFY(CONFIG_NUM_2ND_LEVEL_AGGREGATORS, CAT_2ND_LVL_LIST, (;), CONFIG_2ND_LVL_ISR_TBL_OFFSET);
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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BUILD_ASSERT((CONFIG_NUM_3RD_LEVEL_AGGREGATORS * CONFIG_MAX_IRQ_PER_AGGREGATOR) <=
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BIT(CONFIG_3RD_LEVEL_INTERRUPT_BITS),
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"L3 bits not enough to cover the number of L3 IRQs");
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#define INIT_IRQ_PARENT_OFFSET_3RD(n, d, i, o) \
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IRQ_PARENT_ENTRY_DEFINE(intc_l3_##n, DEVICE_DT_GET_OR_NULL(d), i, o, 3)
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#define CAT_3RD_LVL_LIST(i, base) \
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INIT_IRQ_PARENT_OFFSET_3RD(i, INTC_DT_IRQN_GET(CONFIG_3RD_LVL_INTR_0##i##_OFFSET), \
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CONFIG_3RD_LVL_INTR_0##i##_OFFSET, \
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IRQ_INDEX_TO_OFFSET(i, base))
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LISTIFY(CONFIG_NUM_3RD_LEVEL_AGGREGATORS, CAT_3RD_LVL_LIST, (;), CONFIG_3RD_LVL_ISR_TBL_OFFSET);
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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@ -139,7 +139,7 @@ extern uint8_t z_shared_kernel_page_start;
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/* Called from page fault handler. ptables here is the ptage tables for the
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* faulting user thread and not the current set of page tables
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*/
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extern bool z_x86_kpti_is_access_ok(void *virt, pentry_t *ptables);
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extern bool z_x86_kpti_is_access_ok(void *virt, pentry_t *ptables)
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#endif /* CONFIG_DEMAND_PAGING */
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#endif /* CONFIG_X86_KPTI */
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#endif /* CONFIG_USERSPACE */
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@ -1,7 +0,0 @@
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# MAX78000EVKIT boards configuration
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# Copyright (c) 2025 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MAX78000EVKIT
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select SOC_MAX78000_M4 if BOARD_MAX78000EVKIT_MAX78000_M4
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@ -1,9 +0,0 @@
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# Copyright (c) 2025 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
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board_runner_args(openocd --cmd-pre-init "source [find target/max78000.cfg]")
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board_runner_args(jlink "--device=MAX78000" "--reset-after-load")
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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@ -1,9 +0,0 @@
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# Copyright (c) 2025 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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board:
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name: max78000evkit
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full_name: MAX78000EVKIT
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vendor: adi
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socs:
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- name: max78000
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Binary file not shown.
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Before Width: | Height: | Size: 47 KiB |
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@ -1,308 +0,0 @@
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.. zephyr:board:: max78000evkit
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Overview
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********
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The MAX78000 evaluation kit (EV kit) provides a platform for leveraging the capabilities of the MAX78000 to build
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new generations of artificial intelligence (AI) devices. Onboard hardware includes a digital microphone, a gyroscope/accelerometer, parallel camera module support
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and a 3.5in touch-enabled color TFT display. A secondary display is driven by a power accumulator for tracking
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device power consumption over time. Uncommitted GPIO as well as analog inputs are readily accessible through
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0.1in pin headers. Primary system power as well as UART access is provided by a USB Micro-B connector. A USB
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to SPI bridge provides rapid access to onboard memory, allowing large networks or images to load quickly
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The Zephyr port is running on the MAX78000 MCU.
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.. image:: img/max78000evkit_img1.webp
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:align: center
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:alt: MAX78000 EVKIT
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Hardware
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********
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- MAX78000 MCU:
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- Dual-Core, Low-Power Microcontroller
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- Arm Cortex-M4 Processor with FPU up to 100MHz
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- 512KB Flash and 128KB SRAM
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- Optimized Performance with 16KB Instruction Cache
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- Optional Error Correction Code (ECC-SEC-DED) for SRAM
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- 32-Bit RISC-V Coprocessor up to 60MHz
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- Up to 52 General-Purpose I/O Pins
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- 12-Bit Parallel Camera Interface
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- One I2S Master/Slave for Digital Audio Interface
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- Neural Network Accelerator
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- Highly Optimized for Deep Convolutional Neural Networks
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- 442k 8-Bit Weight Capacity with 1,2,4,8-Bit Weights
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- Programmable Input Image Size up to 1024 x 1024 pixels
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- Programmable Network Depth up to 64 Layers
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- Programmable per Layer Network Channel Widths up to 1024 Channels
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- 1 and 2 Dimensional Convolution Processing
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- Streaming Mode
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- Flexibility to Support Other Network Types, Including MLP and Recurrent Neural Networks
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- Power Management Maximizes Operating Time for Battery Applications
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- Integrated Single-Inductor Multiple-Output (SIMO) Switch-Mode Power Supply (SMPS)
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- 2.0V to 3.6V SIMO Supply Voltage Range
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- Dynamic Voltage Scaling Minimizes Active Core Power Consumption
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- 22.2μA/MHz While Loop Execution at 3.0V from Cache (CM4 Only)
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- Selectable SRAM Retention in Low-Power Modes with Real-Time Clock (RTC) Enabled
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- Security and Integrity
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- Available Secure Boot
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- AES 128/192/256 Hardware Acceleration Engine
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- True Random Number Generator (TRNG) Seed Generator
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Supported Features
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==================
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The ``max78000evkit/max78000/m4`` board target supports the following interfaces:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| CLOCK | on-chip | clock and reset control |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial |
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+-----------+------------+-------------------------------------+
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| TRNG | on-chip | entropy |
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+-----------+------------+-------------------------------------+
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| I2C | on-chip | i2c |
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+-----------+------------+-------------------------------------+
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| DMA | on-chip | dma controller |
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+-----------+------------+-------------------------------------+
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| Watchdog | on-chip | watchdog |
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+-----------+------------+-------------------------------------+
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| SPI | on-chip | spi |
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+-----------+------------+-------------------------------------+
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| ADC | on-chip | adc |
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+-----------+------------+-------------------------------------+
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| Flash | on-chip | flash |
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+-----------+------------+-------------------------------------+
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| Timer | on-chip | pwm |
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+-----------+------------+-------------------------------------+
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| RTC | on-chip | real time clock |
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+-----------+------------+-------------------------------------+
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| Timer | on-chip | counter |
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+-----------+------------+-------------------------------------+
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| W1 | on-chip | one wire master |
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+--------------------------------------------------------------+
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Connections and IOs
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===================
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
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| Name | Name | Settings | Description |
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+===========+===================+===================+==============================================================================================+
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| JP1 | LED1 EN | +---------------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Enables auxiliary LED1 | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Disables auxiliary LED1 | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
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| JP2 | LED2 EN | +---------------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | 1-2 | | | Enables auxiliary LED2 | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
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| | | | Open | | | Disables auxiliary LED2 | |
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
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| JP3 | TRIG1 | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | 1-2 | | | Enables power monitor event trigger 1 | |
|
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | Open | | | Disables power monitor event trigger 1 | |
|
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | |
|
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
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| JP4 | TRIG2 | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | 1-2 | | | Enables power monitor event trigger 2 | |
|
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | Open | | | Disables power monitor event trigger 2 | |
|
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | |
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
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| JP5 | VREGI | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | 1-2 | | | Enables 3V3 VREGI power | |
|
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| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | Open | | | Disables 3V3 VREGI power | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | |
|
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+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
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| JP6 | VREGIA | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | 1-2 | | | Enables 3V3 VREGIA power | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | Open | | | Disables 3V3 VREGIA power | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
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| JP7 | CNN BOOST | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | 1-2 | | | Enables 1V1 boost LDO power | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Disables 1V1 boost LDO power | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP8 | VDDA | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | 1-2 | | | Internal SIMO powers VDDA | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | External LDO powers VDDA | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP9 | VDDIO | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Internal SIMO powers VDDIO | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | External LDO powers VDDIO | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP10 | VDDIOH | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | 1-2 | | | DUT LDO powers VDDIOH | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | AUX LDO powers VDDIOH | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP11 | VCOREB | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
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| | | | 1-2 | | | Internal SIMO powers VCOREB | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | External LDO powers VCOREB | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP12 | VCOREA | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Internal SIMO powers VCOREA | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | External LDO powers VCOREA | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP13 | VREGI PM BYPASS | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Bypasses power monitor shunt | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Enables power monitoring using power accumulator | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP14 | CNN 1V1 | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Connects 1V1 boost LDO to VCOREA | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Disables 1V1 boost LDO | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP15 | VCOREA PM BYPASS | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Bypasses power monitor shunt | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Enables power monitoring using power accumulator | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP16 | VCOREB PM BYPASS | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Bypasses power monitor shunt | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Enables power monitoring using power accumulator | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP17 | VREG_A PM BYPASS | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Bypasses power monitor shunt | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Enables power monitoring using power accumulator | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP18 | RESET EN | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Enables RV JTAG adapter to perform full system reset | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Disables system reset by RV JTAG adapter | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP19 | TFT BL | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Enables main TFT screen backlight | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Disables main TFT screen backlight | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP20 | I2S CLK SEL | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Onboard 12.288MHz oscillator drives I2S clock | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | External 1V8 CMOS LEVEL source drives I2S clock | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP21 | DUT I | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | DUT 3V3 total current monitor point | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | Open | | | Open to insert current meter | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JP22 | USB-SPI/CAM | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2 | | | Enables USB-SPI bridge | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 2-3 | | | Enables camera | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JH1 | UART 0 EN | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | 1-2, 3-4 | | | Enables USB-UART0 bridge, software flow control | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | All Open | | | Disables USB-UART0 bridge, allows reuse of port pins | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
| JH2 | UART 1 EN | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | |All installed | | | Enables USB-UART1 bridge | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | All Open | | | Disables USB-UART1 bridge, allows reuse of port pins | |
|
||||
| | | +---------------+ | +-----------------------------------------------------------------------------------------+ |
|
||||
| | | | |
|
||||
+-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
|
||||
|
||||
Programming and Debugging
|
||||
*************************
|
||||
|
||||
Flashing
|
||||
========
|
||||
|
||||
The MAX78000 MCU can be flashed by connecting an external debug probe to the
|
||||
SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH5.
|
||||
Logic levels are fixed to VDDIO (1.8V).
|
||||
|
||||
Once the debug probe is connected to your host computer, then you can simply run the
|
||||
``west flash`` command to write a firmware image into flash.
|
||||
|
||||
.. note::
|
||||
|
||||
This board uses OpenOCD as the default debug interface. You can also use
|
||||
a Segger J-Link with Segger's native tooling by overriding the runner,
|
||||
appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
|
||||
be connected to the standard 2*5 pin debug connector (JH5) using an
|
||||
appropriate adapter board and cable.
|
||||
|
||||
Debugging
|
||||
=========
|
||||
|
||||
Please refer to the `Flashing`_ section and run the ``west debug`` command
|
||||
instead of ``west flash``.
|
||||
|
||||
References
|
||||
**********
|
||||
|
||||
- `MAX78000EVKIT web page`_
|
||||
|
||||
.. _MAX78000EVKIT web page:
|
||||
https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78000evkit.html
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Analog Devices, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <adi/max32/max78000.dtsi>
|
||||
#include <adi/max32/max78000-pinctrl.dtsi>
|
||||
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
|
||||
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||
|
||||
/ {
|
||||
model = "Analog Devices MAX78000EVKIT";
|
||||
compatible = "adi,max78000evkit";
|
||||
|
||||
chosen {
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,sram = &sram2;
|
||||
zephyr,flash = &flash0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led1: led_1 {
|
||||
gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
|
||||
label = "Green LED";
|
||||
};
|
||||
|
||||
led2: led_2 {
|
||||
gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
|
||||
label = "Red LED";
|
||||
};
|
||||
};
|
||||
|
||||
buttons {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pb1: pb1 {
|
||||
gpios = <&gpio2 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
|
||||
label = "SW2";
|
||||
zephyr,code = <INPUT_KEY_0>;
|
||||
};
|
||||
|
||||
pb2: pb2 {
|
||||
gpios = <&gpio2 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
|
||||
label = "SW3";
|
||||
zephyr,code = <INPUT_KEY_1>;
|
||||
};
|
||||
|
||||
pb_wakeup: pb_wakeup {
|
||||
gpios = <&gpio3 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW
|
||||
| MAX32_GPIO_VSEL_VDDIOH)>;
|
||||
label = "Wakeup";
|
||||
zephyr,code = <INPUT_KEY_WAKEUP>;
|
||||
};
|
||||
};
|
||||
|
||||
/* These aliases are provided for compatibility with samples */
|
||||
aliases {
|
||||
led0 = &led1;
|
||||
led1 = &led2;
|
||||
sw0 = &pb1;
|
||||
sw1 = &pb2;
|
||||
watchdog0 = &wdt0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0a_tx_p0_1 &uart0a_rx_p0_0>;
|
||||
pinctrl-names = "default";
|
||||
current-speed = <115200>;
|
||||
data-bits = <8>;
|
||||
parity = "none";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clk_ipo {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clk_ibro {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&trng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2c0_scl_p0_10 &i2c0_sda_p0_11>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7 &spi0_ss0_p0_4>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&dma0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&w1 {
|
||||
pinctrl-0 = <&owm_io_p0_18 &owm_pe_p0_19>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
identifier: max78000evkit/max78000/m4
|
||||
name: max78000evkit m4
|
||||
vendor: adi
|
||||
type: mcu
|
||||
arch: arm
|
||||
toolchain:
|
||||
- zephyr
|
||||
- gnuarmemb
|
||||
- xtools
|
||||
supported:
|
||||
- adc
|
||||
- counter
|
||||
- dma
|
||||
- flash
|
||||
- gpio
|
||||
- i2c
|
||||
- pwm
|
||||
- serial
|
||||
- spi
|
||||
- trng
|
||||
- w1
|
||||
- watchdog
|
||||
ram: 128
|
||||
flash: 512
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
# Copyright (c) 2025 Analog Devices, Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Enable MPU
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
# Enable GPIO
|
||||
CONFIG_GPIO=y
|
||||
|
||||
# Console
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
|
||||
# Enable UART
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
# MAX78000FTHR boards configuration
|
||||
|
||||
# Copyright (c) 2025 Analog Devices, Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config BOARD_MAX78000FTHR
|
||||
select SOC_MAX78000_M4 if BOARD_MAX78000FTHR_MAX78000_M4
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
# Copyright (c) 2025 Analog Devices, Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
|
||||
board_runner_args(openocd --cmd-pre-init "source [find target/max78000.cfg]")
|
||||
|
||||
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
# Copyright (c) 2025 Analog Devices, Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
board:
|
||||
name: max78000fthr
|
||||
full_name: MAX78000FTHR
|
||||
vendor: adi
|
||||
socs:
|
||||
- name: max78000
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 56 KiB |
|
|
@ -1,210 +0,0 @@
|
|||
.. zephyr:board:: max78000fthr
|
||||
|
||||
Overview
|
||||
********
|
||||
The MAX78000FTHR is a rapid development platform to help engineers quickly implement ultra low-power, artificial
|
||||
intelligence (AI) solutions using the MAX78000 Arm® Cortex®-M4F processor with an integrated Convolutional Neural Network
|
||||
accelerator. The board also includes the MAX20303 PMIC for battery and power management. The form factor is 0.9in x 2.6in
|
||||
dual-row header footprint that is compatible with Adafruit Feather Wing peripheral expansion boards. The board includes a
|
||||
variety of peripherals, such as a CMOS VGA image sensor, digital microphone, low-power stereo audio CODEC, 1MB QSPI
|
||||
SRAM, micro SD card connector, RGB indicator LED, and pushbutton. The MAX78000FTHR provides a poweroptimized flexible
|
||||
platform for quick proof-of-concepts and early software development to enhance time to market.
|
||||
|
||||
The Zephyr port is running on the MAX78000 MCU.
|
||||
|
||||
.. image:: img/max78000fthr_img1.webp
|
||||
:align: center
|
||||
:alt: MAX78000 FTHR
|
||||
|
||||
Hardware
|
||||
********
|
||||
|
||||
- MAX78000 MCU:
|
||||
|
||||
- Dual-Core, Low-Power Microcontroller
|
||||
|
||||
- Arm Cortex-M4 Processor with FPU up to 100MHz
|
||||
- 512KB Flash and 128KB SRAM
|
||||
- Optimized Performance with 16KB Instruction Cache
|
||||
- Optional Error Correction Code (ECC-SEC-DED) for SRAM
|
||||
- 32-Bit RISC-V Coprocessor up to 60MHz
|
||||
- Up to 52 General-Purpose I/O Pins
|
||||
- 12-Bit Parallel Camera Interface
|
||||
- One I2S Master/Slave for Digital Audio Interface
|
||||
|
||||
- Neural Network Accelerator
|
||||
|
||||
- Highly Optimized for Deep Convolutional Neural Networks
|
||||
- 442k 8-Bit Weight Capacity with 1,2,4,8-Bit Weights
|
||||
- Programmable Input Image Size up to 1024 x 1024 pixels
|
||||
- Programmable Network Depth up to 64 Layers
|
||||
- Programmable per Layer Network Channel Widths up to 1024 Channels
|
||||
- 1 and 2 Dimensional Convolution Processing
|
||||
- Streaming Mode
|
||||
- Flexibility to Support Other Network Types, Including MLP and Recurrent Neural Networks
|
||||
|
||||
- Power Management Maximizes Operating Time for Battery Applications
|
||||
|
||||
- Integrated Single-Inductor Multiple-Output (SIMO) Switch-Mode Power Supply (SMPS)
|
||||
- 2.0V to 3.6V SIMO Supply Voltage Range
|
||||
- Dynamic Voltage Scaling Minimizes Active Core Power Consumption
|
||||
- 22.2μA/MHz While Loop Execution at 3.0V from Cache (CM4 Only)
|
||||
- Selectable SRAM Retention in Low-Power Modes with Real-Time Clock (RTC) Enabled
|
||||
|
||||
- Security and Integrity
|
||||
|
||||
- Available Secure Boot
|
||||
- AES 128/192/256 Hardware Acceleration Engine
|
||||
- True Random Number Generator (TRNG) Seed Generator
|
||||
|
||||
Supported Features
|
||||
==================
|
||||
|
||||
The ``max78000fthr/max78000/m4`` board target supports the following interfaces:
|
||||
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Interface | Controller | Driver/Component |
|
||||
+===========+============+=====================================+
|
||||
| NVIC | on-chip | nested vector interrupt controller |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| SYSTICK | on-chip | systick |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| CLOCK | on-chip | clock and reset control |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| GPIO | on-chip | gpio |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| UART | on-chip | serial |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| TRNG | on-chip | entropy |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| I2C | on-chip | i2c |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| DMA | on-chip | dma controller |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Watchdog | on-chip | watchdog |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| SPI | on-chip | spi |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| ADC | on-chip | adc |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Flash | on-chip | flash |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Timer | on-chip | pwm |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| RTC | on-chip | real time clock |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Timer | on-chip | counter |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| W1 | on-chip | one wire master |
|
||||
+--------------------------------------------------------------+
|
||||
|
||||
Connections and IOs
|
||||
===================
|
||||
|
||||
J8 Pinout
|
||||
**********
|
||||
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| Pin | Name | Description |
|
||||
+=========+==========+=================================================================================================+
|
||||
| 1 | RST | Master Reset Signal |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 2 | 3V3 | 3.3V Output. Typically used to provide 3.3V to peripherals connected to the expansion headers. |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 3 | 1V8 | 1.8V Output. Typically used to provide 1.8V to peripherals connected to the expansion headers. |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 4 | GND | Ground |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 5 | P2_3 | GPIO or Analog Input (AIN3 channel). |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 6 | P2_4 | GPIO or Analog Input (AIN4 channel). |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 7 | P1_1 | GPIO or UART2 Tx signal |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 8 | P1_0 | GPIO or UART2 Rx signal |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 9 | MPC1 | GPIO controlled by PMIC through I2C interface. Open drain or push-pull programmable |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 10 | MPC2 | GPIO controlled by PMIC through I2C interface. Open drain or push-pull programmable |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 11 | P0_7 | GPIO or QSPI0 clock signal. Shared with SD card and on-board QSPI SRAM |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 12 | P0_5 | GPIO or QSPI0 MOSI signal. Shared with SD card and on-board QSPI SRAM |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 13 | P0_6 | GPIO or QSPI0 MISO signal. Shared with SD card and on-board QSPI SRAM |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 14 | P2_6 | GPIO or LPUART Rx signal |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 15 | P2_7 | GPIO or LPUART Tx signal |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
| 16 | GND | Ground |
|
||||
+---------+----------+-------------------------------------------------------------------------------------------------+
|
||||
|
||||
J4 Pinout
|
||||
**********
|
||||
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| Pin | Name | Description |
|
||||
+=========+==========+===========================================================================================================+
|
||||
| 1 | SYS | SYS Switched Connection to the Battery. This is the primary system power supply and automatically |
|
||||
| | | switches between the battery voltage and the USB supply when available. |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 2 | PWR | Turns off the PMIC if shorted to Ground for 13 seconds. Hard power-down button. |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 3 | VBUS | USB VBUS Signal. This can be used as a 5V supply when connected to USB. This pin can also be |
|
||||
| | | used as an input to power the board. |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 4 | P1_6 | GPIO |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 5 | MPC3 | GPIO controlled by PMIC through the I2C interface. Open drain or push-pull programmable. |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 6 | P0_9 | GPIO or QSPI0 SDIO3 signal. Shared with SD card and on-board QSPI SRAM. |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 7 | P0_8 | GPIO or QSPI0 SDIO2 signal. Shared with SD Card and on-board QSPI SRAM. |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 8 | P0_11 | GPIO or QSPI0 slave select signal |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 9 | P0_19 | GPIO |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 10 | P3_1 | GPIO or Wake-up signal. This pin is 3.3V only. |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 11 | P0_16 | GPIO or I2C1 SCL signal. An on-board level shifter allows selecting 1.8V or 3.3V operation through |
|
||||
| | | R15 or R20 resistors. Do not populate both. |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
| 12 | P0_17 | GPIO or I2C1 SDA signal. An on-board level shifter allows selecting 1.8V or 3.3V operation through |
|
||||
| | | R15 or R20 resistors. Do not populate both. |
|
||||
+---------+----------+-----------------------------------------------------------------------------------------------------------+
|
||||
|
||||
Programming and Debugging
|
||||
*************************
|
||||
|
||||
Flashing
|
||||
========
|
||||
|
||||
The MAX32625 microcontroller on the board is preprogrammed with DAPLink firmware.
|
||||
It allows debugging and programming of the MAX78000 Arm core over USB.
|
||||
|
||||
Once the debug probe is connected to your host computer, then you can simply run the
|
||||
``west flash`` command to write a firmware image into flash.
|
||||
|
||||
.. note::
|
||||
|
||||
This board uses OpenOCD as the default debug interface. You can also use
|
||||
a Segger J-Link with Segger's native tooling by overriding the runner,
|
||||
appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
|
||||
be connected to the standard 2*5 pin debug connector (JH5) using an
|
||||
appropriate adapter board and cable.
|
||||
|
||||
Debugging
|
||||
=========
|
||||
|
||||
Please refer to the `Flashing`_ section and run the ``west debug`` command
|
||||
instead of ``west flash``.
|
||||
|
||||
References
|
||||
**********
|
||||
|
||||
- `MAX78000FTHR web page`_
|
||||
|
||||
.. _MAX78000FTHR web page:
|
||||
https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78000fthr.html
|
||||
|
|
@ -1,130 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Analog Devices, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <adi/max32/max78000.dtsi>
|
||||
#include <adi/max32/max78000-pinctrl.dtsi>
|
||||
#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
|
||||
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||
|
||||
/ {
|
||||
model = "Analog Devices MAX78000FTHR";
|
||||
compatible = "adi,max78000fthr";
|
||||
|
||||
chosen {
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,sram = &sram2;
|
||||
zephyr,flash = &flash0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led1: led_1 {
|
||||
gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
|
||||
label = "Red LED";
|
||||
};
|
||||
|
||||
led2: led_2 {
|
||||
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
label = "Green LED";
|
||||
};
|
||||
|
||||
led3: led_3 {
|
||||
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
|
||||
label = "Blue LED";
|
||||
};
|
||||
};
|
||||
|
||||
buttons {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pb1: pb1 {
|
||||
gpios = <&gpio0 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
|
||||
label = "SW1";
|
||||
zephyr,code = <INPUT_KEY_0>;
|
||||
};
|
||||
|
||||
pb2: pb2 {
|
||||
gpios = <&gpio1 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
|
||||
label = "SW2";
|
||||
zephyr,code = <INPUT_KEY_1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* These aliases are provided for compatibility with samples */
|
||||
aliases {
|
||||
led0 = &led1;
|
||||
led1 = &led2;
|
||||
sw0 = &pb1;
|
||||
sw1 = &pb2;
|
||||
watchdog0 = &wdt0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0a_tx_p0_1 &uart0a_rx_p0_0>;
|
||||
pinctrl-names = "default";
|
||||
current-speed = <115200>;
|
||||
data-bits = <8>;
|
||||
parity = "none";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clk_ipo {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clk_ibro {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&trng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2c0_scl_p0_10 &i2c0_sda_p0_11>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7 &spi0_ss0_p0_4>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&dma0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&w1 {
|
||||
pinctrl-0 = <&owm_io_p0_6 &owm_pe_p0_7>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
identifier: max78000fthr/max78000/m4
|
||||
name: max78000fthr m4
|
||||
vendor: adi
|
||||
type: mcu
|
||||
arch: arm
|
||||
toolchain:
|
||||
- zephyr
|
||||
- gnuarmemb
|
||||
- xtools
|
||||
supported:
|
||||
- adc
|
||||
- counter
|
||||
- dma
|
||||
- flash
|
||||
- gpio
|
||||
- i2c
|
||||
- pwm
|
||||
- serial
|
||||
- spi
|
||||
- trng
|
||||
- w1
|
||||
- watchdog
|
||||
ram: 128
|
||||
flash: 512
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
# Copyright (c) 2025 Analog Devices, Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Enable MPU
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
# Enable GPIO
|
||||
CONFIG_GPIO=y
|
||||
|
||||
# Console
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
|
||||
# Enable UART
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_UART_INTERRUPT_DRIVEN=y
|
||||
|
|
@ -140,6 +140,7 @@
|
|||
};
|
||||
|
||||
&spi0 {
|
||||
compatible = "ambiq,spi";
|
||||
pinctrl-0 = <&spi0_default>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
|
||||
|
|
@ -148,6 +149,7 @@
|
|||
};
|
||||
|
||||
&i2c3 {
|
||||
compatible = "ambiq,i2c";
|
||||
pinctrl-0 = <&i2c3_default>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
|
|
@ -194,6 +196,7 @@
|
|||
};
|
||||
|
||||
&adc0 {
|
||||
compatible = "ambiq,adc";
|
||||
pinctrl-0 = <&adc0_default>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -118,6 +118,7 @@
|
|||
};
|
||||
|
||||
&spi0 {
|
||||
compatible = "ambiq,spi";
|
||||
pinctrl-0 = <&spi0_default>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
|
||||
|
|
@ -126,6 +127,7 @@
|
|||
};
|
||||
|
||||
&i2c3 {
|
||||
compatible = "ambiq,i2c";
|
||||
pinctrl-0 = <&i2c3_default>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
|
|
@ -172,6 +174,7 @@
|
|||
};
|
||||
|
||||
&adc0 {
|
||||
compatible = "ambiq,adc";
|
||||
pinctrl-0 = <&adc0_default>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -90,6 +90,7 @@
|
|||
};
|
||||
|
||||
&i2c0 {
|
||||
compatible = "ambiq,i2c";
|
||||
pinctrl-0 = <&i2c0_default>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
|
|
@ -99,6 +100,7 @@
|
|||
};
|
||||
|
||||
&spi1 {
|
||||
compatible = "ambiq,spi";
|
||||
pinctrl-0 = <&spi1_default>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
|
||||
|
|
|
|||
|
|
@ -76,6 +76,7 @@
|
|||
};
|
||||
|
||||
&adc0 {
|
||||
compatible = "ambiq,adc";
|
||||
pinctrl-0 = <&adc0_default>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
|
@ -95,6 +96,7 @@
|
|||
};
|
||||
|
||||
&iom0_i2c {
|
||||
compatible = "ambiq,i2c";
|
||||
pinctrl-0 = <&i2c0_default>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
|
|
@ -104,6 +106,7 @@
|
|||
};
|
||||
|
||||
&iom1_spi {
|
||||
compatible = "ambiq,spi";
|
||||
pinctrl-0 = <&spi1_default>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
|
||||
|
|
|
|||
|
|
@ -1,20 +0,0 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_SOC_SERIES_STM32L0X OR CONFIG_SOC_SERIES_STM32L1X)
|
||||
board_runner_args(openocd "--cmd-erase=stm32l1x mass_erase 0")
|
||||
elseif(CONFIG_SOC_SERIES_STM32L4X OR
|
||||
CONFIG_SOC_SERIES_STM32L5X OR
|
||||
CONFIG_SOC_SERIES_STM32U5X OR
|
||||
CONFIG_SOC_SERIES_STM32WBX OR
|
||||
CONFIG_SOC_SERIES_STM32G0X OR
|
||||
CONFIG_SOC_SERIES_STM32G4X)
|
||||
board_runner_args(openocd "--cmd-erase=stm32l4x mass_erase 0")
|
||||
elseif(CONFIG_SOC_SERIES_STM32F0X OR
|
||||
CONFIG_SOC_SERIES_STM32F1X OR
|
||||
CONFIG_SOC_SERIES_STM32F3X)
|
||||
board_runner_args(openocd "--cmd-erase=stm32f1x mass_erase 0")
|
||||
elseif(CONFIG_SOC_SERIES_STM32F2X OR
|
||||
CONFIG_SOC_SERIES_STM32F4X OR
|
||||
CONFIG_SOC_SERIES_STM32F7X)
|
||||
board_runner_args(openocd "--cmd-erase=stm32f2x mass_erase 0")
|
||||
endif()
|
||||
|
|
@ -20,6 +20,3 @@ board_finalize_runner_args(openocd
|
|||
--cmd-load "${OPENOCD_CMD_LOAD_DEFAULT}"
|
||||
--cmd-verify "${OPENOCD_CMD_VERIFY_DEFAULT}"
|
||||
)
|
||||
|
||||
# Manufacturer common options
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/openocd-stm32.board.cmake)
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
};
|
||||
|
||||
chosen {
|
||||
zephyr,sram = &sram1;
|
||||
zephyr,sram = &sram0;
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,flash = &flash0;
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
};
|
||||
|
||||
chosen {
|
||||
zephyr,sram = &sram1;
|
||||
zephyr,sram = &sram0;
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,flash = &flash0;
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
};
|
||||
|
||||
chosen {
|
||||
zephyr,sram = &sram1;
|
||||
zephyr,sram = &sram0;
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,flash = &flash0;
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
};
|
||||
|
||||
&mtimer {
|
||||
reg = <0x90000 0x8 0x90008 0x8>;
|
||||
reg = <0x90000 0x10>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
};
|
||||
|
||||
&mtimer {
|
||||
reg = <0x90000 0x8 0x90008 0x8>;
|
||||
reg = <0x90000 0x10>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
compatible = "espressif,esp32";
|
||||
|
||||
chosen {
|
||||
zephyr,sram = &sram1;
|
||||
zephyr,sram = &sram0;
|
||||
zephyr,ipc_shm = &shm0;
|
||||
zephyr,ipc = &ipm0;
|
||||
zephyr,flash = &flash0;
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
};
|
||||
|
||||
chosen {
|
||||
zephyr,sram = &sram1;
|
||||
zephyr,sram = &sram0;
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,flash = &flash0;
|
||||
|
|
|
|||
|
|
@ -40,7 +40,6 @@ This boards include models of some of the nRF54L15 SOC peripherals:
|
|||
* AAR (Accelerated Address Resolver)
|
||||
* CCM (AES CCM mode encryption)
|
||||
* CLOCK (Clock control)
|
||||
* CRACEN (Crypto Accelerator Engine)
|
||||
* DPPI (Distributed Programmable Peripheral Interconnect)
|
||||
* ECB (AES electronic codebook mode encryption)
|
||||
* EGU (Event Generator Unit)
|
||||
|
|
@ -50,6 +49,7 @@ This boards include models of some of the nRF54L15 SOC peripherals:
|
|||
* PPIB (PPI Bridge)
|
||||
* RADIO
|
||||
* RRAMC (Resistive RAM Controller)
|
||||
* RTC (Real Time Counter)
|
||||
* TEMP (Temperature sensor)
|
||||
* TIMER
|
||||
* UARTE (UART with Easy DMA)
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@
|
|||
|
||||
rng: rng {
|
||||
status = "okay";
|
||||
compatible = "nordic,nrf-cracen-ctrdrbg";
|
||||
compatible = "zephyr,native-posix-rng";
|
||||
};
|
||||
|
||||
psa_rng: psa-rng {
|
||||
|
|
|
|||
|
|
@ -10,8 +10,8 @@ CONFIG_HW_STACK_PROTECTION=y
|
|||
CONFIG_GPIO=y
|
||||
|
||||
# Enable UART driver
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_SERIAL=n
|
||||
|
||||
# Enable console
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
CONFIG_CONSOLE=n
|
||||
CONFIG_UART_CONSOLE=n
|
||||
|
|
|
|||
|
|
@ -108,13 +108,13 @@ The FRDM-MCXN947 board configuration supports the following hardware features:
|
|||
Dual Core samples
|
||||
*****************
|
||||
|
||||
+-----------+-------------------+----------------------+
|
||||
| Core | Boot Address | Comment |
|
||||
+===========+===================+======================+
|
||||
| CPU0 | 0x10000000[1856K] | primary core flash |
|
||||
+-----------+-------------------+----------------------+
|
||||
| CPU1 | 0x101d0000[192K] | secondary core flash |
|
||||
+-----------+-------------------+----------------------+
|
||||
+-----------+------------------+----------------------+
|
||||
| Core | Boot Address | Comment |
|
||||
+===========+==================+======================+
|
||||
| CPU0 | 0x10000000[992K] | primary core flash |
|
||||
+-----------+------------------+----------------------+
|
||||
| CPU1 | 0x101ce000[200K] | secondary core flash |
|
||||
+-----------+------------------+----------------------+
|
||||
|
||||
+----------+------------------+-----------------------+
|
||||
| Memory | Address[Size] | Comment |
|
||||
|
|
|
|||
|
|
@ -149,10 +149,6 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/*
|
||||
* Partition sizes must be aligned
|
||||
* to the flash memory sector size of 8KB.
|
||||
*/
|
||||
boot_partition: partition@0 {
|
||||
label = "mcuboot";
|
||||
reg = <0x00000000 DT_SIZE_K(80)>;
|
||||
|
|
@ -162,15 +158,15 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
|
|||
*/
|
||||
slot0_partition: partition@14000 {
|
||||
label = "image-0";
|
||||
reg = <0x00014000 DT_SIZE_K(888)>;
|
||||
reg = <0x00014000 DT_SIZE_K(884)>;
|
||||
};
|
||||
slot1_partition: partition@F2000 {
|
||||
slot1_partition: partition@F1000 {
|
||||
label = "image-1";
|
||||
reg = <0x000F2000 DT_SIZE_K(888)>;
|
||||
reg = <0x000F1000 DT_SIZE_K(884)>;
|
||||
};
|
||||
cpu1_partition: partition@1D0000 {
|
||||
cpu1_partition: partition@1CE000 {
|
||||
label = "cpu1-image";
|
||||
reg = <0x001D0000 DT_SIZE_K(192)>;
|
||||
reg = <0x001CE000 DT_SIZE_K(200)>;
|
||||
};
|
||||
/* storage_partition is placed in WINBOND flash memory*/
|
||||
};
|
||||
|
|
|
|||
|
|
@ -32,16 +32,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
pinmux_lpi2c0: pinmux_lpi2c0 {
|
||||
group0 {
|
||||
pinmux = <LPI2C0_SCL_PTA19>,
|
||||
<LPI2C0_SDA_PTA18>;
|
||||
drive-strength = "low";
|
||||
slew-rate = "fast";
|
||||
drive-open-drain;
|
||||
};
|
||||
};
|
||||
|
||||
pinmux_lpi2c1: pinmux_lpi2c1 {
|
||||
group0 {
|
||||
pinmux = <LPI2C1_SCL_PTB5>,
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2024-2025 NXP
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -22,8 +22,6 @@
|
|||
zephyr,flash = &w25q512jvfiq;
|
||||
zephyr,console = &flexcomm3;
|
||||
zephyr,shell-uart = &flexcomm3;
|
||||
zephyr,flash-controller = &w25q512jvfiq;
|
||||
zephyr,code-partition = &slot0_partition;
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
|
|||
|
|
@ -89,37 +89,36 @@ NXP prioritizes enabling the superset board with NXP's Full Platform Support for
|
|||
Zephyr. Therefore, the mimxrt1064_evk board may have additional features
|
||||
already supported, which can also be re-used on this mimxrt1040_evk board:
|
||||
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| Interface | Controller | Driver/Component |
|
||||
+===========+============+=================================================+
|
||||
| NVIC | on-chip | nested vector interrupt controller |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| SYSTICK | on-chip | systick |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| GPIO | on-chip | gpio |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| UART | on-chip | serial port-polling; |
|
||||
| | | serial port-interrupt |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| PWM | on-chip | pwm |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| ADC | on-chip | adc |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| SPI | on-chip | spi |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| DMA | on-chip | dma |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| I2C | on-chip | i2c |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| GPT | on-chip | gpt |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| DISPLAY | on-chip | eLCDIF. Tested with |
|
||||
| | | :ref:`rk043fn02h_ct`, and |
|
||||
| | | :ref:`rk043fn66hs_ctg` shields |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
| UART | NXP IW61x | M.2 WIFI/BT module |
|
||||
| | | (select :kconfig:option:`CONFIG_BT_NXP_NW612`) |
|
||||
+-----------+------------+-------------------------------------------------+
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Interface | Controller | Driver/Component |
|
||||
+===========+============+=====================================+
|
||||
| NVIC | on-chip | nested vector interrupt controller |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| SYSTICK | on-chip | systick |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| GPIO | on-chip | gpio |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| UART | on-chip | serial port-polling; |
|
||||
| | | serial port-interrupt |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| PWM | on-chip | pwm |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| ADC | on-chip | adc |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| SPI | on-chip | spi |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| DMA | on-chip | dma |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| I2C | on-chip | i2c |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| GPT | on-chip | gpt |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| DISPLAY | on-chip | eLCDIF. Tested with |
|
||||
| | | :ref:`rk043fn02h_ct`, and |
|
||||
| | | :ref:`rk043fn66hs_ctg` shields |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| UART | NXP NW61x | M.2 WIFI/BT module |
|
||||
+-----------+------------+-------------------------------------+
|
||||
|
||||
The default configuration can be found in
|
||||
:zephyr_file:`boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig`
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright 2018-2022, 2025 NXP
|
||||
# Copyright 2018-2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
|
@ -12,7 +12,7 @@ endif()
|
|||
|
||||
if(CONFIG_NXP_IMXRT_BOOT_HEADER)
|
||||
zephyr_library()
|
||||
if((${BOARD_REVISION} STREQUAL "B") OR (${BOARD_REVISION} STREQUAL "C"))
|
||||
if(${BOARD_REVISION} STREQUAL "B")
|
||||
set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c)
|
||||
set(BOARD_NAME evkbmimxrt1060)
|
||||
elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_NOR_ENABLED)
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ board_runner_args(pyocd "--target=mimxrt1060")
|
|||
board_runner_args(jlink "--device=MIMXRT1062xxx6A")
|
||||
board_runner_args(linkserver "--device=MIMXRT1062xxxxA:EVK-MIMXRT1060")
|
||||
|
||||
if(("${BOARD_QUALIFIERS}" MATCHES "qspi") OR ("${BOARD_REVISION}" STREQUAL "B") OR ("${BOARD_REVISION}" STREQUAL "C"))
|
||||
if(("${BOARD_QUALIFIERS}" MATCHES "qspi") OR ("${BOARD_REVISION}" STREQUAL "B"))
|
||||
board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI")
|
||||
elseif ("${BOARD_QUALIFIERS}" MATCHES "hyperflash")
|
||||
board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=HyperFlash")
|
||||
|
|
|
|||
|
|
@ -9,8 +9,7 @@ boards:
|
|||
- name: "hyperflash"
|
||||
revision:
|
||||
format: "letter"
|
||||
default: "C"
|
||||
default: "A"
|
||||
revisions:
|
||||
- name: "A"
|
||||
- name: "B"
|
||||
- name: "C"
|
||||
|
|
|
|||
|
|
@ -316,28 +316,8 @@ The MIMXRT1060 SoC has eight UARTs. ``LPUART1`` is configured for the console,
|
|||
``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the
|
||||
remaining are not used.
|
||||
|
||||
Board Revisions and Targets
|
||||
***************************
|
||||
|
||||
There are three revisions of this board.
|
||||
|
||||
Rev A:
|
||||
|
||||
* Initial version
|
||||
|
||||
Rev B:
|
||||
|
||||
* adds the M.2 connector for Wi-Fi/BLE
|
||||
* adds audio expansion connector J23
|
||||
* USER LED1 changed to GPIO1 pin 8
|
||||
|
||||
Rev C:
|
||||
|
||||
* Replaces audio codec WM8960(EOL) to WM8962
|
||||
* Replaces 32.768 KHz oscillator from ASH7K-32.768KHz-T(EOL)to ASH7KW-32.768KHZ-L-T
|
||||
* Replaces motion sensor from FXOS8700CQ(EOL) to FXLS8974CFR3
|
||||
* Re-assigns Bluetooth Audio PCM with dedicated I2S2
|
||||
* Re-assigns Bluetooth interface UART_CTS, UART_RTS to hardware PIN
|
||||
Board Targets
|
||||
*************
|
||||
|
||||
This board has two variants that can be targeted,
|
||||
depending on which flash to set as ``zephyr,flash``:
|
||||
|
|
@ -407,28 +387,10 @@ Flashing
|
|||
|
||||
Here is an example for the :zephyr:code-sample:`hello_world` application.
|
||||
|
||||
.. tabs::
|
||||
|
||||
.. group-tab:: i.MX RT1060 Rev A
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: mimxrt1060_evk@A//qspi
|
||||
:goals: flash
|
||||
|
||||
.. group-tab:: i.MX RT1060 Rev B
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: mimxrt1060_evk@B//qspi
|
||||
:goals: flash
|
||||
|
||||
.. group-tab:: i.MX RT1060 Rev C (default)
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: mimxrt1060_evk@C//qspi
|
||||
:goals: flash
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: mimxrt1060_evk//qspi
|
||||
:goals: flash
|
||||
|
||||
Open a serial terminal, reset the board (press the SW9 button), and you should
|
||||
see the following message in the terminal:
|
||||
|
|
@ -443,29 +405,10 @@ Debugging
|
|||
|
||||
Here is an example for the :zephyr:code-sample:`hello_world` application.
|
||||
|
||||
.. tabs::
|
||||
|
||||
.. group-tab:: i.MX RT1060 Rev A
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: mimxrt1060_evk@A//qspi
|
||||
:goals: debug
|
||||
|
||||
.. group-tab:: i.MX RT1060 Rev B
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: mimxrt1060_evk@B//qspi
|
||||
:goals: debug
|
||||
|
||||
.. group-tab:: i.MX RT1060 Rev C (default)
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: mimxrt1060_evk@C//qspi
|
||||
:goals: debug
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: mimxrt1060_evk//qspi
|
||||
:goals: debug
|
||||
|
||||
Open a serial terminal, step through the application in your debugger, and you
|
||||
should see the following message in the terminal:
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
identifier: mimxrt1060_evk@A/mimxrt1062/qspi
|
||||
identifier: mimxrt1060_evk/mimxrt1062/qspi
|
||||
name: NXP MIMXRT1060-EVK
|
||||
type: mcu
|
||||
arch: arm
|
||||
|
|
|
|||
|
|
@ -14,20 +14,20 @@ toolchain:
|
|||
ram: 32768
|
||||
flash: 8192
|
||||
supported:
|
||||
- adc
|
||||
- arduino_gpio
|
||||
- arduino_i2c
|
||||
- arduino_serial
|
||||
- arduino_spi
|
||||
- can
|
||||
- counter
|
||||
- display
|
||||
- dma
|
||||
- gpio
|
||||
- i2c
|
||||
- netif:eth
|
||||
- sdhc
|
||||
- spi
|
||||
- usbd
|
||||
- usb_device
|
||||
- dma
|
||||
- can
|
||||
- watchdog
|
||||
- adc
|
||||
vendor: nxp
|
||||
|
|
|
|||
|
|
@ -1,15 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Whisper.ai
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* FLEXPWM not routed to LED on this EVK */
|
||||
&flexpwm2_pwm3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&green_led {
|
||||
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||
label = "User LED1";
|
||||
};
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
#
|
||||
# Copyright (c) 2022, Whisper.ai
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
identifier: mimxrt1060_evk@C/mimxrt1062/qspi
|
||||
name: NXP MIMXRT1060-EVKC
|
||||
type: mcu
|
||||
arch: arm
|
||||
toolchain:
|
||||
- zephyr
|
||||
- gnuarmemb
|
||||
- xtools
|
||||
ram: 32768
|
||||
flash: 8192
|
||||
supported:
|
||||
- adc
|
||||
- arduino_gpio
|
||||
- arduino_i2c
|
||||
- arduino_serial
|
||||
- arduino_spi
|
||||
- can
|
||||
- counter
|
||||
- display
|
||||
- dma
|
||||
- gpio
|
||||
- i2c
|
||||
- netif:eth
|
||||
- sdhc
|
||||
- spi
|
||||
- usbd
|
||||
- watchdog
|
||||
vendor: nxp
|
||||
|
|
@ -107,68 +107,67 @@ this board with new support for Zephyr features. Note that this table
|
|||
covers two boards: the RT1170 EVK (``mimxrt1170_evk//cm7/cm4``), and
|
||||
RT1170 EVKB (``mimxrt1170_evk@B//cm7/cm4``)
|
||||
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| Interface | Controller | Driver/Component | RT1170 EVK | RT1170 EVKB |
|
||||
+===========+============+================================================+=================+=================+
|
||||
| NVIC | on-chip | nested vector interrupt controller | Supported | Supported |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| SYSTICK | on-chip | systick | Supported | Supported |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| GPIO | on-chip | gpio | Supported | Supported |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| COUNTER | on-chip | gpt | Supported | Supported |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| TIMER | on-chip | gpt | Supported | Supported |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| CAN | on-chip | flexcan | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| SPI | on-chip | spi | Supported (M7) | Supported |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| I2C | on-chip | i2c | Supported | Supported |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| PWM | on-chip | pwm | Supported | Supported |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| ADC | on-chip | adc | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| UART | on-chip | serial port-polling; | Supported | Supported |
|
||||
| | | serial port-interrupt; | | |
|
||||
| | | serial port-async | | |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| DMA | on-chip | dma | Supported | Supported |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| WATCHDOG | on-chip | watchdog | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| ENET | on-chip | ethernet - 10/100M | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| ENET1G | on-chip | ethernet - 10/100/1000M | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| SAI | on-chip | i2s | Supported | No support |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| USB | on-chip | USB Device | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| HWINFO | on-chip | Unique device serial number | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| DISPLAY | on-chip | eLCDIF; MIPI-DSI. Tested with | Supported (M7) | Supported (M7) |
|
||||
| | | :ref:`rk055hdmipi4m`, | | |
|
||||
| | | :ref:`rk055hdmipi4ma0`, | | |
|
||||
| | | and :ref:`g1120b0mipi` shields | | |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| ACMP | on-chip | sensor | Supported | No support |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| CAAM RNG | on-chip | entropy | Supported (M7) | No support |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| FLEXSPI | on-chip | flash programming | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| SDHC | on-chip | SD host controller | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| PIT | on-chip | pit | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| VIDEO | on-chip | CSI; MIPI CSI-2 Rx. Tested with | Supported (M7) | Supported (M7) |
|
||||
| | | :ref:`nxp_btb44_ov5640` shield | | |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
| UART | NXP IW61x | M.2 WIFI/BT module | Unsupported | Supported (M7) |
|
||||
| | | (select :kconfig:option:`CONFIG_BT_NXP_NW612`) | | |
|
||||
+-----------+------------+------------------------------------------------+-----------------+-----------------+
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| Interface | Controller | Driver/Component | RT1170 EVK | RT1170 EVKB |
|
||||
+===========+============+=====================================+=================+=================+
|
||||
| NVIC | on-chip | nested vector interrupt controller | Supported | Supported |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| SYSTICK | on-chip | systick | Supported | Supported |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| GPIO | on-chip | gpio | Supported | Supported |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| COUNTER | on-chip | gpt | Supported | Supported |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| TIMER | on-chip | gpt | Supported | Supported |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| CAN | on-chip | flexcan | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| SPI | on-chip | spi | Supported (M7) | Supported |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| I2C | on-chip | i2c | Supported | Supported |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| PWM | on-chip | pwm | Supported | Supported |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| ADC | on-chip | adc | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| UART | on-chip | serial port-polling; | Supported | Supported |
|
||||
| | | serial port-interrupt; | | |
|
||||
| | | serial port-async | | |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| DMA | on-chip | dma | Supported | Supported |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| WATCHDOG | on-chip | watchdog | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| ENET | on-chip | ethernet - 10/100M | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| ENET1G | on-chip | ethernet - 10/100/1000M | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| SAI | on-chip | i2s | Supported | No support |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| USB | on-chip | USB Device | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| HWINFO | on-chip | Unique device serial number | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| DISPLAY | on-chip | eLCDIF; MIPI-DSI. Tested with | Supported (M7) | Supported (M7) |
|
||||
| | | :ref:`rk055hdmipi4m`, | | |
|
||||
| | | :ref:`rk055hdmipi4ma0`, | | |
|
||||
| | | and :ref:`g1120b0mipi` shields | | |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| ACMP | on-chip | sensor | Supported | No support |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| CAAM RNG | on-chip | entropy | Supported (M7) | No support |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| FLEXSPI | on-chip | flash programming | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| SDHC | on-chip | SD host controller | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| PIT | on-chip | pit | Supported (M7) | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| VIDEO | on-chip | CSI; MIPI CSI-2 Rx. Tested with | Supported (M7) | Supported (M7) |
|
||||
| | | :ref:`nxp_btb44_ov5640` shield | | |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
| UART | NXP NW61x | M.2 WIFI/BT module | Unsupported | Supported (M7) |
|
||||
+-----------+------------+-------------------------------------+-----------------+-----------------+
|
||||
|
||||
The default configuration can be found in the defconfig files:
|
||||
:zephyr_file:`boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig`
|
||||
|
|
|
|||
|
|
@ -19,5 +19,5 @@ board_runner_args(linkserver "--core=cm7")
|
|||
board_runner_args(jlink "--device=MIMXRT1189xxx8_M7" "--speed=4000" "--no-reset" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm7.jlinkscript" "--tool-opt=-ir")
|
||||
endif()
|
||||
|
||||
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
|
||||
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
|
||||
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
|
||||
|
|
|
|||
|
|
@ -183,19 +183,18 @@ Build and flash applications as usual (see :ref:`build_an_application` and
|
|||
Configuring a Debug Probe
|
||||
=========================
|
||||
|
||||
LinkServer is the default runner for this board.
|
||||
A debug probe is used for both flashing and debugging the board. This board is
|
||||
configured by default to use the :ref:`mcu-link-cmsis-onboard-debug-probe`.
|
||||
The :ref:`pyocd-debug-host-tools` do not yet support programming the
|
||||
external flashes on this board. Use one of the other supported debug probes
|
||||
below.
|
||||
configured by default to use the :ref:`mcu-link-cmsis-onboard-debug-probe`,
|
||||
however the :ref:`pyocd-debug-host-tools` do not yet support programming the
|
||||
external flashes on this board so you must reconfigure the board for one of the
|
||||
following debug probes instead.
|
||||
|
||||
.. _Using J-Link RT1180:
|
||||
|
||||
Using J-Link
|
||||
------------
|
||||
|
||||
Please ensure to use a version of JLINK above V7.94g and jumper JP5 is installed if using
|
||||
Please ensure used JLINK above V7.94g and jumper JP5 installed if using
|
||||
external jlink plus on J37 as debugger.
|
||||
|
||||
When debugging cm33 core, need to ensure the SW5 on "0100" mode.
|
||||
|
|
@ -213,7 +212,7 @@ EVK.
|
|||
Using Linkserver
|
||||
----------------
|
||||
|
||||
Please ensure to use a version of Linkserver above V1.5.30 and jumper JP5 is uninstalled (default setting).
|
||||
Please ensure used linkserver above V1.5.30 and jumper JP5 uninstalled.
|
||||
|
||||
When debugging cm33 core, need to ensure the SW5 on "0100" mode.
|
||||
When debugging cm7 core, need to ensure the SW5 on "0001" mode.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2023-2024 NXP
|
||||
* Copyright 2023 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -344,8 +344,6 @@
|
|||
readoc = "1-4-4";
|
||||
writeoc = "1-4-4";
|
||||
has-32k-erase;
|
||||
max-program-buffer-size = <256>;
|
||||
write-block-size = <1>;
|
||||
status = "okay";
|
||||
|
||||
partitions {
|
||||
|
|
|
|||
|
|
@ -62,8 +62,6 @@ The boards support the following hardware features:
|
|||
+-----------+------------+-------------------------------------+
|
||||
| eMIOS | on-chip | pwm |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| QSPI | on-chip | flash |
|
||||
+-----------+------------+-------------------------------------+
|
||||
|
||||
Other hardware features are not currently supported by the port.
|
||||
|
||||
|
|
@ -174,12 +172,6 @@ EDMA
|
|||
The EDMA modules feature four EDMA3 instances: Instance 0 with 32 channels,
|
||||
and instances 1, 4, and 5, each with 16 channels.
|
||||
|
||||
External Flash
|
||||
==============
|
||||
|
||||
The on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller
|
||||
port A1. This board configuration selects it as the default flash controller.
|
||||
|
||||
Programming and Debugging
|
||||
*************************
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@
|
|||
*/
|
||||
|
||||
#include "s32z2xxdc2_s32z270_pinctrl.dtsi"
|
||||
#include <zephyr/dt-bindings/qspi/nxp-s32-qspi.h>
|
||||
|
||||
&swt0 {
|
||||
status = "okay";
|
||||
|
|
@ -59,69 +58,3 @@
|
|||
&sar_adc1 {
|
||||
vref-mv = <1800>;
|
||||
};
|
||||
|
||||
&qspi0 {
|
||||
pinctrl-0 = <&qspi0_default>;
|
||||
pinctrl-names = "default";
|
||||
data-rate = "DDR";
|
||||
column-space = <3>;
|
||||
word-addressable;
|
||||
hold-time-2x;
|
||||
a-dll-freq-enable;
|
||||
a-dll-ref-counter = <2>;
|
||||
a-dll-resolution = <2>;
|
||||
a-dll-coarse-delay = <2>;
|
||||
a-dll-fine-delay = <2>;
|
||||
a-dll-mode = "AUTO UPDATE";
|
||||
a-rx-clock-source = "EXTERNAL DQS";
|
||||
ahb-buffers-masters = <0 1 2 3>;
|
||||
ahb-buffers-sizes = <256 256 256 256>;
|
||||
ahb-buffers-all-masters;
|
||||
status = "okay";
|
||||
|
||||
sfp_mdad {
|
||||
compatible = "nxp,s32-qspi-sfp-mdad";
|
||||
|
||||
mdad_0: mdad_0 {
|
||||
domain-id = <0>;
|
||||
secure-attribute = <NXP_S32_QSPI_SECURE>;
|
||||
};
|
||||
};
|
||||
|
||||
sfp_frad {
|
||||
compatible = "nxp,s32-qspi-sfp-frad";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
frad_0: frad@0 {
|
||||
reg = <0x0 DT_SIZE_M(512)>;
|
||||
master-domain-acp-policy = <NXP_S32_QSPI_SECURE>;
|
||||
};
|
||||
};
|
||||
|
||||
s26hs512t: s26hs512t@0 {
|
||||
compatible = "nxp,s32-qspi-hyperflash";
|
||||
reg = <0>;
|
||||
jedec-id = [00 34 00 7b 00 1a 00 0f 00 90];
|
||||
device-id-word-addr = <0x800>;
|
||||
size = <DT_SIZE_M(512)>;
|
||||
write-block-size = <2>;
|
||||
read-latency-cycles = <16>;
|
||||
max-program-buffer-size = <256>;
|
||||
vcc-mv = <1800>;
|
||||
drive-strength-ohm = <27>;
|
||||
ppw-sectors-addr-mapping = "LOW";
|
||||
status = "okay";
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
storage_partition: partition@0 {
|
||||
label = "storage";
|
||||
reg = <0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -127,25 +127,4 @@
|
|||
drive-open-drain;
|
||||
};
|
||||
};
|
||||
|
||||
qspi0_default: qspi0_default {
|
||||
group1 {
|
||||
pinmux = <PI4_QSPI_0_DATA_A_O0>, <PH14_QSPI_0_DATA_A_O1>,
|
||||
<PI8_QSPI_0_DATA_A_O2>, <PI1_QSPI_0_DATA_A_O3>,
|
||||
<PI5_QSPI_0_DATA_A_O4>, <PH15_QSPI_0_DATA_A_O5>,
|
||||
<PI7_QSPI_0_DATA_A_O6>, <PI0_QSPI_0_DATA_A_O7>,
|
||||
<PI6_QSPI_0_DQS_A_O>;
|
||||
output-enable;
|
||||
input-enable;
|
||||
};
|
||||
group2 {
|
||||
pinmux = <PH13_QSPI_0_CS_A0>, <PI9_QSPI_0_CS_A1>,
|
||||
<PI2_QSPI_0_CK_A_B>, <PI3_QSPI_0_CK_A>;
|
||||
output-enable;
|
||||
};
|
||||
group3 {
|
||||
pinmux = <PH12_QSPI_0_INTA_B>;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
zephyr,sram = &dram0;
|
||||
zephyr,flash = &cram0;
|
||||
zephyr,canbus = &canxl0;
|
||||
zephyr,flash-controller = &s26hs512t;
|
||||
};
|
||||
|
||||
aliases {
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
zephyr,sram = &dram1;
|
||||
zephyr,flash = &cram1;
|
||||
zephyr,canbus = &flexcan0;
|
||||
zephyr,flash-controller = &s26hs512t;
|
||||
};
|
||||
|
||||
aliases {
|
||||
|
|
|
|||
|
|
@ -45,8 +45,6 @@ features:
|
|||
+-----------+------------+-------------------------------------+
|
||||
| UART | on-chip | serial port |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Mailbox | on-chip | IPC Mailbox |
|
||||
+-----------+------------+-------------------------------------+
|
||||
|
||||
Devices
|
||||
========
|
||||
|
|
|
|||
|
|
@ -56,8 +56,6 @@ The phyboard_lyra/am6234/m4 configuration supports the following hardware featur
|
|||
+-----------+------------+-------------------------------------+
|
||||
| UART | on-chip | serial |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Mailbox | on-chip | IPC Mailbox |
|
||||
+-----------+------------+-------------------------------------+
|
||||
|
||||
Other hardware features are not currently supported by the port.
|
||||
|
||||
|
|
|
|||
|
|
@ -5,100 +5,72 @@ PJRC TEENSY 4
|
|||
|
||||
Overview
|
||||
********
|
||||
|
||||
The Teensy is a complete USB-based microcontroller development system, in a
|
||||
very small footprint, capable of implementing many types of projects. All
|
||||
programming is done via the USB port.
|
||||
|
||||
.. tabs::
|
||||
|
||||
.. group-tab:: Teensy 4.0
|
||||
.. figure:: teensy40.jpg
|
||||
:align: center
|
||||
:alt: TEENSY40
|
||||
|
||||
.. figure:: img/teensy40.jpg
|
||||
:align: center
|
||||
:alt: TEENSY40
|
||||
TEENSY40 (Credit: https://www.pjrc.com)
|
||||
|
||||
(Credit: https://www.pjrc.com)
|
||||
.. figure:: teensy41.jpg
|
||||
:align: center
|
||||
:alt: TEENSY41
|
||||
|
||||
.. group-tab:: Teensy 4.1
|
||||
|
||||
.. figure:: img/teensy41.jpg
|
||||
:align: center
|
||||
:alt: TEENSY41
|
||||
|
||||
(Credit: https://www.pjrc.com)
|
||||
TEENSY41 (Credit: https://www.pjrc.com)
|
||||
|
||||
Hardware
|
||||
********
|
||||
|
||||
.. tabs::
|
||||
Teensy 4.0:
|
||||
|
||||
.. group-tab:: Teensy 4.0
|
||||
- MIMXRT1062DVL6A MCU (600 MHz, 1024 KB on-chip memory)
|
||||
- 16 Mbit QSPI Flash
|
||||
- LED
|
||||
- USB 2.0 host connector
|
||||
|
||||
- MIMXRT1062DVL6A MCU (600 MHz, 1024 KB on-chip memory)
|
||||
- 16 Mbit QSPI Flash
|
||||
- User LED
|
||||
- USB 2.0 host connector
|
||||
Teensy 4.1:
|
||||
|
||||
See the `Teensy 4.0 Website`_ for a complete hardware description.
|
||||
- MIMXRT1062DVJ6A MCU (600 MHz, 1024 KB on-chip memory)
|
||||
- 64 Mbit QSPI Flash
|
||||
- LED
|
||||
- USB 2.0 host connector
|
||||
- USB 2.0 OTG connector
|
||||
- 10/100 Mbit/s Ethernet PHY
|
||||
- TF socket for SD card
|
||||
|
||||
.. group-tab:: Teensy 4.1
|
||||
|
||||
- MIMXRT1062DVJ6A MCU (600 MHz, 1024 KB on-chip memory)
|
||||
- 64 Mbit QSPI Flash
|
||||
- User LED
|
||||
- USB 2.0 host connector
|
||||
- USB 2.0 OTG connector
|
||||
- 10/100 Mbit/s Ethernet transceiver
|
||||
- TF socket for SD card
|
||||
|
||||
To connect an Ethernet cable, additional `Teensy 4.1 Ethernet Kit`_ is required.
|
||||
|
||||
See the `Teensy 4.1 Website`_ for a complete hardware description.
|
||||
|
||||
For more information, check the `i.MX RT1060 Datasheet`_.
|
||||
See the `Teensy 4.0 Website`_ for a complete hardware description.
|
||||
|
||||
Supported Features
|
||||
==================
|
||||
|
||||
The Teensy 4.0 board configuration supports the following hardware
|
||||
The teensy40 board configuration supports the following hardware
|
||||
features:
|
||||
|
||||
+-----------+------------+----------------------+
|
||||
| Interface | Controller | Driver/Component |
|
||||
+===========+============+======================+
|
||||
| ADC | on-chip | adc |
|
||||
+-----------+------------+----------------------+
|
||||
| CLOCK | on-chip | clock_control |
|
||||
+-----------+------------+----------------------+
|
||||
| FLASH | on-chip | flash |
|
||||
+-----------+------------+----------------------+
|
||||
| GPIO | on-chip | gpio |
|
||||
+-----------+------------+----------------------+
|
||||
| I2C | on-chip | i2c |
|
||||
+-----------+------------+----------------------+
|
||||
| I2S | on-chip | i2s |
|
||||
+-----------+------------+----------------------+
|
||||
| NVIC | on-chip | arch/arm |
|
||||
+-----------+------------+----------------------+
|
||||
| PWM | on-chip | pwm |
|
||||
+-----------+------------+----------------------+
|
||||
| RTC | on-chip | system clock |
|
||||
+-----------+------------+----------------------+
|
||||
| SPI | on-chip | spi |
|
||||
+-----------+------------+----------------------+
|
||||
| CAN | on-chip | can |
|
||||
+-----------+------------+----------------------+
|
||||
| UART | on-chip | serial |
|
||||
+-----------+------------+----------------------+
|
||||
| USB | on-chip | usb |
|
||||
+-----------+------------+----------------------+
|
||||
| TRNG | on-chip | entropy |
|
||||
+-----------+------------+----------------------+
|
||||
| WDT | on-chip | watchdog |
|
||||
+-----------+------------+----------------------+
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Interface | Controller | Driver/Component |
|
||||
+===========+============+=====================================+
|
||||
| NVIC | on-chip | nested vector interrupt controller |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| SYSTICK | on-chip | systick |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| GPIO | on-chip | gpio |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| I2C | on-chip | i2c |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| UART | on-chip | serial port-polling; |
|
||||
| | | serial port-interrupt |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| USB | on-chip | USB device |
|
||||
+-----------+------------+-------------------------------------+
|
||||
|
||||
The Teensy 4.1 board configuration supports additional hardware
|
||||
The default configuration can be found in
|
||||
:zephyr_file:`boards/pjrc/teensy4/teensy40_defconfig`
|
||||
|
||||
The teensy41 board configuration supports additional hardware
|
||||
features:
|
||||
|
||||
+-----------+------------+-------------------------------------+
|
||||
|
|
@ -109,7 +81,10 @@ features:
|
|||
| ENET | on-chip | ethernet |
|
||||
+-----------+------------+-------------------------------------+
|
||||
|
||||
Other hardware features have not been enabled yet for this board.
|
||||
The default configuration can be found in
|
||||
:zephyr_file:`boards/pjrc/teensy4/teensy41_defconfig`
|
||||
|
||||
Other hardware features are not currently supported by the port.
|
||||
|
||||
Connections and IOs
|
||||
===================
|
||||
|
|
@ -229,97 +204,23 @@ Programming and Debugging
|
|||
|
||||
Flashing
|
||||
========
|
||||
Build applications as usual (see :ref:`build_an_application` for more details).
|
||||
|
||||
Both the Teensy 4.0 and Teensy 4.1 ship with a dedicated bootloader chip,
|
||||
which supports flashing using USB. This allows easy flashing of new images,
|
||||
but does not support debugging the device.
|
||||
Flash hex-file with the documented tools:
|
||||
|
||||
#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application.
|
||||
.. _Teensy flash tools:
|
||||
https://www.pjrc.com/teensy/loader.html
|
||||
|
||||
.. tabs::
|
||||
Debugging
|
||||
=========
|
||||
Console output is mapped to teensy pins 0 (RX1) and 1 (TX1). Connect a usb-to-serial adapter
|
||||
to use this serial console. Use the following settings with your serial terminal of choice (minicom, putty,
|
||||
etc.):
|
||||
|
||||
.. group-tab:: Teensy 4.0
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/basic/blinky
|
||||
:board: teensy40
|
||||
:goals: build
|
||||
:compact:
|
||||
|
||||
.. group-tab:: Teensy 4.1
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/basic/blinky
|
||||
:board: teensy41
|
||||
:goals: build
|
||||
:compact:
|
||||
|
||||
#. Connect the board to your host computer using USB.
|
||||
|
||||
#. Tap the reset button to enter bootloader mode.
|
||||
Red LED blinks.
|
||||
|
||||
#. Flash the image.
|
||||
|
||||
.. tabs::
|
||||
|
||||
.. group-tab:: Teensy 4.0
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/basic/blinky
|
||||
:board: teensy40
|
||||
:goals: flash
|
||||
:compact:
|
||||
|
||||
.. group-tab:: Teensy 4.1
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/basic/blinky
|
||||
:board: teensy41
|
||||
:goals: flash
|
||||
:compact:
|
||||
|
||||
#. You should see the orange LED blink.
|
||||
|
||||
Configuring a Console
|
||||
=====================
|
||||
|
||||
.. tabs::
|
||||
|
||||
.. group-tab:: UART-Console
|
||||
|
||||
By default console output is mapped to teensy pins 0 (RX1) and 1 (TX1). Connect a usb-to-serial adapter
|
||||
to use this serial console. Use the following settings with your serial terminal of choice (minicom, putty,
|
||||
etc.):
|
||||
|
||||
- Speed: 115200
|
||||
- Data: 8 bits
|
||||
- Parity: None
|
||||
- Stop bits: 1
|
||||
|
||||
.. group-tab:: USB-Console
|
||||
|
||||
By mapping the console output to USB, a usb-to-serial adapter is no longer required.
|
||||
Utilizing the :ref:`snippet-cdc-acm-console` and a config option will enable this feature.
|
||||
|
||||
#. If application code doesn´t enable USB device support, this must be done via Kconfig option.
|
||||
|
||||
.. code-block:: kconfig
|
||||
|
||||
CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=y
|
||||
|
||||
#. Build application including the snippet.
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/basic/blinky
|
||||
:snippets: cdc-acm-console
|
||||
:board: teensy41
|
||||
:goals: flash
|
||||
:compact:
|
||||
|
||||
#. After application startup a serial device named like
|
||||
``tty.usbmodem14203`` should appear on your host computer.
|
||||
You can use e.g. ``Serial Monitor`` plugin for VScode to monitor.
|
||||
- Speed: 115200
|
||||
- Data: 8 bits
|
||||
- Parity: None
|
||||
- Stop bits: 1
|
||||
|
||||
References
|
||||
**********
|
||||
|
|
@ -329,11 +230,14 @@ References
|
|||
.. _Teensy 4.0 Website:
|
||||
https://www.pjrc.com/store/teensy40.html
|
||||
|
||||
.. _Teensy 4.1 Website:
|
||||
https://www.pjrc.com/store/teensy41.html
|
||||
.. _Teensy Schematics:
|
||||
https://www.pjrc.com/teensy/schematic.html
|
||||
|
||||
.. _Teensy 4.1 Ethernet Kit:
|
||||
https://www.pjrc.com/store/ethernet_kit.html
|
||||
.. _i.MX RT1060 Website:
|
||||
https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060
|
||||
|
||||
.. _i.MX RT1060 Datasheet:
|
||||
https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1060CEC.pdf
|
||||
|
||||
.. _i.MX RT1060 Reference Manual:
|
||||
https://www.nxp.com/webapp/Download?colCode=IMXRT1060RM
|
||||
|
|
|
|||
|
Before Width: | Height: | Size: 38 KiB After Width: | Height: | Size: 38 KiB |
|
Before Width: | Height: | Size: 58 KiB After Width: | Height: | Size: 58 KiB |
|
|
@ -108,6 +108,8 @@ The below features are currently supported on Zephyr OS for EK-RA6E2 board:
|
|||
+-----------+------------+----------------------+
|
||||
| FLASH | on-chip | flash |
|
||||
+-----------+------------+----------------------+
|
||||
| QSPI | on-chip | qspi flash |
|
||||
+-----------+------------+----------------------+
|
||||
|
||||
Other hardware features are currently not supported by the port.
|
||||
|
||||
|
|
|
|||
|
|
@ -46,4 +46,16 @@
|
|||
<RA_PSEL(RA_PSEL_GPT1, 4, 8)>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_default: qspi_default {
|
||||
group1 {
|
||||
/* QSPICLK QSSL QIO0 QIO1 QIO2 QIO3 */
|
||||
psels = <RA_PSEL(RA_PSEL_QSPI, 1, 0)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 1, 12)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 1, 2)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 1, 1)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 1, 4)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 1, 3)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -178,3 +178,16 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi0 {
|
||||
pinctrl-0 = <&qspi_default>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
at25sf128a: ra-qspi-nor@60000000 {
|
||||
compatible = "renesas,ra-qspi-nor";
|
||||
reg = <0x60000000 DT_SIZE_M(16)>;
|
||||
status = "okay";
|
||||
write-block-size = <1>;
|
||||
erase-block-size = <4096>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -110,6 +110,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M3 board:
|
|||
+-----------+------------+----------------------+
|
||||
| FLASH | on-chip | flash |
|
||||
+-----------+------------+----------------------+
|
||||
| QSPI | on-chip | qspi flash |
|
||||
+-----------+------------+----------------------+
|
||||
|
||||
Other hardware features are currently not supported by the port.
|
||||
|
||||
|
|
|
|||
|
|
@ -53,4 +53,16 @@
|
|||
<RA_PSEL(RA_PSEL_GPT1, 4, 6)>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_default: qspi_default {
|
||||
group1 {
|
||||
/* QSPICLK QSSL QIO0 QIO1 QIO2 QIO3 */
|
||||
psels = <RA_PSEL(RA_PSEL_QSPI, 3, 5)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 6)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 7)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 8)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 9)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 10)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -173,3 +173,16 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi0 {
|
||||
pinctrl-0 = <&qspi_default>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
mx25l25645g: ra-qspi-nor@60000000 {
|
||||
compatible = "renesas,ra-qspi-nor";
|
||||
reg = <0x60000000 DT_SIZE_M(32)>;
|
||||
status = "okay";
|
||||
write-block-size = <1>;
|
||||
erase-block-size = <4096>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -115,6 +115,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M4 board:
|
|||
+-----------+------------+----------------------+
|
||||
| ENTROPY | on-chip | entropy |
|
||||
+-----------+------------+----------------------+
|
||||
| QSPI | on-chip | qspi flash |
|
||||
+-----------+------------+----------------------+
|
||||
|
||||
Other hardware features are currently not supported by the port.
|
||||
|
||||
|
|
|
|||
|
|
@ -46,4 +46,16 @@
|
|||
<RA_PSEL(RA_PSEL_GPT1, 4, 6)>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_default: qspi_default {
|
||||
group1 {
|
||||
/* QSPICLK QSSL QIO0 QIO1 QIO2 QIO3 */
|
||||
psels = <RA_PSEL(RA_PSEL_QSPI, 3, 5)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 6)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 7)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 8)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 9)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 10)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -161,3 +161,16 @@
|
|||
&trng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi0 {
|
||||
pinctrl-0 = <&qspi_default>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
mx25l25645g: ra-qspi-nor@60000000 {
|
||||
compatible = "renesas,ra-qspi-nor";
|
||||
reg = <0x60000000 DT_SIZE_M(32)>;
|
||||
status = "okay";
|
||||
write-block-size = <1>;
|
||||
erase-block-size = <4096>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -115,6 +115,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M5 board:
|
|||
+-----------+------------+----------------------+
|
||||
| ENTROPY | on-chip | entropy |
|
||||
+-----------+------------+----------------------+
|
||||
| QSPI | on-chip | qspi flash |
|
||||
+-----------+------------+----------------------+
|
||||
|
||||
Other hardware features are currently not supported by the port.
|
||||
|
||||
|
|
|
|||
|
|
@ -53,4 +53,16 @@
|
|||
<RA_PSEL(RA_PSEL_GPT1, 4, 6)>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_default: qspi_default {
|
||||
group1 {
|
||||
/* QSPICLK QSSL QIO0 QIO1 QIO2 QIO3 */
|
||||
psels = <RA_PSEL(RA_PSEL_QSPI, 3, 5)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 6)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 7)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 8)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 9)>,
|
||||
<RA_PSEL(RA_PSEL_QSPI, 3, 10)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -165,3 +165,16 @@
|
|||
&trng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi0 {
|
||||
pinctrl-0 = <&qspi_default>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
mx25l25645g: ra-qspi-nor@60000000 {
|
||||
compatible = "renesas,ra-qspi-nor";
|
||||
reg = <0x60000000 DT_SIZE_M(32)>;
|
||||
status = "okay";
|
||||
write-block-size = <1>;
|
||||
erase-block-size = <4096>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -123,6 +123,8 @@ The below features are currently supported on Zephyr OS for EK-RA8D1 board:
|
|||
+--------------+------------+-----------------------------------+
|
||||
| SDHC | on-chip | sdhc |
|
||||
+--------------+------------+-----------------------------------+
|
||||
| OSPI | on-chip | ospi flash |
|
||||
+--------------+------------+-----------------------------------+
|
||||
|
||||
**Note:**
|
||||
|
||||
|
|
|
|||
|
|
@ -261,4 +261,22 @@
|
|||
drive-strength = "highspeed-high";
|
||||
};
|
||||
};
|
||||
|
||||
ospi0_default: ospi0_default {
|
||||
group1 {
|
||||
/* sclk dqs sio0-7 */
|
||||
psels = <RA_PSEL(RA_PSEL_OSPI, 8, 8)>, <RA_PSEL(RA_PSEL_OSPI, 8, 1)>,
|
||||
<RA_PSEL(RA_PSEL_OSPI, 1, 0)>, <RA_PSEL(RA_PSEL_OSPI, 8, 3)>,
|
||||
<RA_PSEL(RA_PSEL_OSPI, 1, 3)>, <RA_PSEL(RA_PSEL_OSPI, 1, 1)>,
|
||||
<RA_PSEL(RA_PSEL_OSPI, 1, 2)>, <RA_PSEL(RA_PSEL_OSPI, 8, 0)>,
|
||||
<RA_PSEL(RA_PSEL_OSPI, 8, 2)>, <RA_PSEL(RA_PSEL_OSPI, 8, 4)>;
|
||||
drive-strength = "highspeed-high";
|
||||
};
|
||||
group2 {
|
||||
/* cs1 rst ecsint1 */
|
||||
psels = <RA_PSEL(RA_PSEL_OSPI, 1, 4)>, <RA_PSEL(RA_PSEL_OSPI, 1, 6)>,
|
||||
<RA_PSEL(RA_PSEL_OSPI, 1, 5)>;
|
||||
drive-strength = "high";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <renesas/ra/ra8/r7fa8d1bhecbd.dtsi>
|
||||
#include <zephyr/dt-bindings/flash_controller/xspi.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input-event-codes.h>
|
||||
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
|
||||
|
|
@ -111,6 +112,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pll2 {
|
||||
status = "okay";
|
||||
clocks = <&xtal>;
|
||||
div = <2>;
|
||||
mul = <80 0>;
|
||||
pll2p {
|
||||
status = "okay";
|
||||
freq = <DT_FREQ_M(400)>;
|
||||
div = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&sciclk {
|
||||
clocks = <&pllp>;
|
||||
|
|
@ -130,6 +142,12 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&octaspiclk {
|
||||
clocks = <&pll2p>;
|
||||
div = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ioport0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -300,3 +318,43 @@ zephyr_mipi_dsi: &mipi_dsi {};
|
|||
renesas_mipi_i2c: &iic1{};
|
||||
|
||||
pmod_sd_shield: &sdhc1 {};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-0 = <&ospi0_default>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
s28hl512t: s28hl512t@90000000 {
|
||||
compatible = "renesas,ra-ospi-b-nor";
|
||||
protocol-mode = <XSPI_OCTO_MODE>;
|
||||
data-rate = <XSPI_DTR_TRANSFER>;
|
||||
ospi-max-frequency = <DT_FREQ_M(200)>;
|
||||
reg = <0x90000000 DT_SIZE_M(64)>;
|
||||
write-block-size = <1>;
|
||||
pages_layout: pages_layout {
|
||||
pages_layout_4k: pages_layout_4k {
|
||||
pages-count = <32>;
|
||||
pages-size = <DT_SIZE_K(4)>;
|
||||
};
|
||||
pages_layout_128k: pages_layout_128k {
|
||||
pages-count = <1>;
|
||||
pages-size = <DT_SIZE_K(128)>;
|
||||
};
|
||||
pages_layout_256k: pages_layout_256k {
|
||||
pages-count = <255>;
|
||||
pages-size = <DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
status = "okay";
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "nor";
|
||||
reg = <0x00000000 DT_SIZE_M(64)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@ The below features are currently supported on Zephyr OS for EK-RA8M1 board:
|
|||
+-----------+------------+----------------------+
|
||||
| SDHC | on-chip | sdhc |
|
||||
+-----------+------------+----------------------+
|
||||
| OSPI | on-chip | ospi flash |
|
||||
+-----------+------------+----------------------+
|
||||
|
||||
**Note:**
|
||||
|
||||
|
|
|
|||
|
|
@ -138,4 +138,22 @@
|
|||
drive-strength = "highspeed-high";
|
||||
};
|
||||
};
|
||||
|
||||
ospi0_default: ospi0_default {
|
||||
group1 {
|
||||
/* sclk dqs sio0-7 */
|
||||
psels = <RA_PSEL(RA_PSEL_OSPI, 8, 8)>, <RA_PSEL(RA_PSEL_OSPI, 8, 1)>,
|
||||
<RA_PSEL(RA_PSEL_OSPI, 1, 0)>, <RA_PSEL(RA_PSEL_OSPI, 8, 3)>,
|
||||
<RA_PSEL(RA_PSEL_OSPI, 1, 3)>, <RA_PSEL(RA_PSEL_OSPI, 1, 1)>,
|
||||
<RA_PSEL(RA_PSEL_OSPI, 1, 2)>, <RA_PSEL(RA_PSEL_OSPI, 8, 0)>,
|
||||
<RA_PSEL(RA_PSEL_OSPI, 8, 2)>, <RA_PSEL(RA_PSEL_OSPI, 8, 4)>;
|
||||
drive-strength = "highspeed-high";
|
||||
};
|
||||
group2 {
|
||||
/* cs1 rst ecsint1 */
|
||||
psels = <RA_PSEL(RA_PSEL_OSPI, 1, 4)>, <RA_PSEL(RA_PSEL_OSPI, 1, 6)>,
|
||||
<RA_PSEL(RA_PSEL_OSPI, 1, 5)>;
|
||||
drive-strength = "high";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
|
||||
#include <renesas/ra/ra8/r7fa8m1ahecbd.dtsi>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <zephyr/dt-bindings/flash_controller/xspi.h>
|
||||
#include <zephyr/dt-bindings/adc/adc.h>
|
||||
#include <zephyr/dt-bindings/input/input-event-codes.h>
|
||||
#include "ek_ra8m1-pinctrl.dtsi"
|
||||
|
|
@ -148,6 +149,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pll2 {
|
||||
status = "okay";
|
||||
clocks = <&xtal>;
|
||||
div = <2>;
|
||||
mul = <80 0>;
|
||||
pll2p {
|
||||
status = "okay";
|
||||
freq = <DT_FREQ_M(400)>;
|
||||
div = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&sciclk {
|
||||
clocks = <&pllp>;
|
||||
|
|
@ -161,6 +173,12 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&octaspiclk {
|
||||
clocks = <&pll2p>;
|
||||
div = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ioport0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -349,3 +367,43 @@ pmod_header: &pmod1_header {};
|
|||
};
|
||||
|
||||
pmod_sd_shield: &sdhc0 {};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-0 = <&ospi0_default>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
s28hl512t: s28hl512t@90000000 {
|
||||
compatible = "renesas,ra-ospi-b-nor";
|
||||
protocol-mode = <XSPI_OCTO_MODE>;
|
||||
data-rate = <XSPI_DTR_TRANSFER>;
|
||||
ospi-max-frequency = <DT_FREQ_M(200)>;
|
||||
reg = <0x90000000 DT_SIZE_M(64)>;
|
||||
write-block-size = <1>;
|
||||
pages_layout: pages_layout {
|
||||
pages_layout_4k: pages_layout_4k {
|
||||
pages-count = <32>;
|
||||
pages-size = <DT_SIZE_K(4)>;
|
||||
};
|
||||
pages_layout_128k: pages_layout_128k {
|
||||
pages-count = <1>;
|
||||
pages-size = <DT_SIZE_K(128)>;
|
||||
};
|
||||
pages_layout_256k: pages_layout_256k {
|
||||
pages-count = <255>;
|
||||
pages-size = <DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
status = "okay";
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "nor";
|
||||
reg = <0x00000000 DT_SIZE_M(64)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,74 +0,0 @@
|
|||
/* Copyright (c) 2024 sensry.io */
|
||||
/* SPDX-License-Identifier: Apache-2.0 */
|
||||
|
||||
#include <zephyr/dt-bindings/pinctrl/sy1xx-pinctrl.h>
|
||||
|
||||
&pinctrl {
|
||||
|
||||
/* UART0 */
|
||||
/omit-if-no-ref/ uart0_tx: uart0_tx {
|
||||
pinmux = <SY1XX_UART0_PAD_CFG0 SY1XX_PAD(0)>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart0_rx: uart0_rx {
|
||||
pinmux = <SY1XX_UART0_PAD_CFG0 SY1XX_PAD(1)>;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
/omit-if-no-ref/ uart1_tx: uart1_tx {
|
||||
pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(0)>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart1_rx: uart1_rx {
|
||||
pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(1)>;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart1_cts: uart1_cts {
|
||||
pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(2)>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart1_rts: uart1_rts {
|
||||
pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(3)>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
/* UART2 */
|
||||
/omit-if-no-ref/ uart2_tx: uart2_tx {
|
||||
pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(0)>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart2_rx: uart2_rx {
|
||||
pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(1)>;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart2_cts: uart2_cts {
|
||||
pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(2)>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/ uart2_rts: uart2_rts {
|
||||
pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(3)>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_tx &uart0_rx>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-0 = <&uart1_tx &uart1_rx &uart1_cts &uart1_rts>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2_tx &uart2_rx &uart2_cts &uart2_rts>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
|
@ -4,7 +4,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <sensry/ganymed-sy1xx.dtsi>
|
||||
#include "ganymed_bob_sy120-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <sensry/ganymed-sy1xx.dtsi>
|
||||
#include "ganymed_bob_sy120-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ Hardware
|
|||
- Transmit power: up to +20 dBm
|
||||
- Operation frequency: 2.4 GHz
|
||||
- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz).
|
||||
- On board devices:
|
||||
- On board sensors:
|
||||
|
||||
- Silicon Labs Si7021 relative humidity & temperature sensor
|
||||
- Silicon Labs Si7210 hall effect sensor
|
||||
|
|
@ -25,7 +25,6 @@ Hardware
|
|||
- TDK InvenSense ICM-20689 6-axis inertial measurement sensor
|
||||
- Vishay VEML6035 ambient light sensor
|
||||
- Bosch BMP384 pressure sensor with internal temperature sensor
|
||||
- MX25R3235F 32 Mbit SPI data flash
|
||||
|
||||
For more information about the EFR32MG24 SoC and BRD2601B board, refer to these
|
||||
documents:
|
||||
|
|
@ -40,35 +39,33 @@ Supported Features
|
|||
|
||||
The board configuration supports the following hardware features:
|
||||
|
||||
+-----------+------------+------------------------------------+
|
||||
| Interface | Controller | Driver/Component |
|
||||
+===========+============+====================================+
|
||||
| MPU | on-chip | memory protection unit |
|
||||
+-----------+------------+------------------------------------+
|
||||
| NVIC | on-chip | nested vector interrupt controller |
|
||||
+-----------+------------+------------------------------------+
|
||||
| SYSTICK | on-chip | systick |
|
||||
+-----------+------------+------------------------------------+
|
||||
| SYSRTC | on-chip | counter, timer |
|
||||
+-----------+------------+------------------------------------+
|
||||
| MSC | on-chip | flash memory |
|
||||
+-----------+------------+------------------------------------+
|
||||
| GPIO | on-chip | gpio |
|
||||
+-----------+------------+------------------------------------+
|
||||
| EUSART | on-chip | serial, spi |
|
||||
+-----------+------------+------------------------------------+
|
||||
| USART | on-chip | serial, spi |
|
||||
+-----------+------------+------------------------------------+
|
||||
| LDMA | on-chip | dma |
|
||||
+-----------+------------+------------------------------------+
|
||||
| SE | on-chip | entropy |
|
||||
+-----------+------------+------------------------------------+
|
||||
| WDOG | on-chip | watchdog |
|
||||
+-----------+------------+------------------------------------+
|
||||
| I2C | on-chip | i2c |
|
||||
+-----------+------------+------------------------------------+
|
||||
| RADIO | on-chip | bluetooth |
|
||||
+-----------+------------+------------------------------------+
|
||||
+-----------+------------+-------------------------------------+
|
||||
| Interface | Controller | Driver/Component |
|
||||
+===========+============+=====================================+
|
||||
| MPU | on-chip | memory protection unit |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| NVIC | on-chip | nested vector interrupt controller |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| SYSTICK | on-chip | systick |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| COUNTER | on-chip | stimer |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| FLASH | on-chip | flash memory |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| GPIO | on-chip | gpio |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| UART | on-chip | serial |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| DMA | on-chip | ldma |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| TRNG | on-chip | semailbox |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| WATCHDOG | on-chip | watchdog |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| I2C(M/S) | on-chip | i2c |
|
||||
+-----------+------------+-------------------------------------+
|
||||
| RADIO | on-chip | bluetooth |
|
||||
+-----------+------------+-------------------------------------+
|
||||
|
||||
Other hardware features are currently not supported by the port.
|
||||
|
||||
|
|
@ -76,37 +73,23 @@ Connections and IOs
|
|||
===================
|
||||
|
||||
In the following table, the column **Name** contains Pin names. For example, PA2
|
||||
means Pin number 2 on Port A, as used in the board's datasheets and manuals.
|
||||
means Pin number 2 on PORTA, as used in the board's datasheets and manuals.
|
||||
|
||||
+------+--------------+---------------------+
|
||||
| Name | Function | Usage |
|
||||
+======+==============+=====================+
|
||||
| PA4 | GPIO | LED0 |
|
||||
+------+--------------+---------------------+
|
||||
| PB0 | GPIO | LED1 |
|
||||
+------+--------------+---------------------+
|
||||
| PD2 | GPIO | LED2 |
|
||||
+------+--------------+---------------------+
|
||||
| PB2 | GPIO | Push Button 0 |
|
||||
+------+--------------+---------------------+
|
||||
| PB3 | GPIO | Push Button 1 |
|
||||
+------+--------------+---------------------+
|
||||
| PA5 | USART0_TX | UART Console |
|
||||
+------+--------------+---------------------+
|
||||
| PA6 | USART0_RX | UART Console |
|
||||
+------+--------------+---------------------+
|
||||
| PC3 | EUSART1_TX | SPI bus: flash, IMU |
|
||||
+------+--------------+---------------------+
|
||||
| PC2 | EUSART1_RX | SPI bus: flash, IMU |
|
||||
+------+--------------+---------------------+
|
||||
| PC1 | EUSART1_SCLK | SPI bus: flash, IMU |
|
||||
+------+--------------+---------------------+
|
||||
| PC0 | EUSART1_CS | SPI bus: flash |
|
||||
+------+--------------+---------------------+
|
||||
| PC4 | I2C0_SCL | I2C bus |
|
||||
+------+--------------+---------------------+
|
||||
| PC5 | I2C0_SDA | I2C bus |
|
||||
+------+--------------+---------------------+
|
||||
+-------+-------------+-------------------------------------+
|
||||
| Name | Function | Usage |
|
||||
+=======+=============+=====================================+
|
||||
| PA4 | GPIO | LED0 |
|
||||
+-------+-------------+-------------------------------------+
|
||||
| PB0 | GPIO | LED1 |
|
||||
+-------+-------------+-------------------------------------+
|
||||
| PB2 | GPIO | Push Button 0 |
|
||||
+-------+-------------+-------------------------------------+
|
||||
| PB3 | GPIO | Push Button 1 |
|
||||
+-------+-------------+-------------------------------------+
|
||||
| PA5 | USART0_TX | UART Console VCOM_TX US0_TX |
|
||||
+-------+-------------+-------------------------------------+
|
||||
| PA6 | USART0_RX | UART Console VCOM_RX US0_RX |
|
||||
+-------+-------------+-------------------------------------+
|
||||
|
||||
The default configuration can be found in
|
||||
:zephyr_file:`boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b_defconfig`
|
||||
|
|
|
|||
|
|
@ -20,19 +20,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
eusart1_default: eusart1_default {
|
||||
group0 {
|
||||
pins = <EUSART1_TX_PC3>, <EUSART1_SCLK_PC1>;
|
||||
drive-push-pull;
|
||||
output-high;
|
||||
};
|
||||
group1 {
|
||||
pins = <EUSART1_RX_PC2>;
|
||||
input-enable;
|
||||
silabs,input-filter;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0_default: i2c0_default {
|
||||
group0 {
|
||||
pins = <I2C0_SCL_PC4>, <I2C0_SDA_PC5>;
|
||||
|
|
|
|||
|
|
@ -124,29 +124,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&eusart1 {
|
||||
compatible = "silabs,eusart-spi";
|
||||
pinctrl-0 = <&eusart1_default>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <&gpioc 0 GPIO_ACTIVE_LOW>;
|
||||
clock-frequency = <4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
mx25r32: mx25r3235f@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <80000000>;
|
||||
size = <0x2000000>;
|
||||
jedec-id = [c2 28 16];
|
||||
has-dpd;
|
||||
dpd-wakeup-sequence = <30000 20 35000>;
|
||||
mxicy,mx25r-power-mode = "low-power";
|
||||
zephyr,pm-device-runtime-auto;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_default>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -37,13 +37,6 @@
|
|||
interrupt-names = "soft0", "timer0";
|
||||
};
|
||||
|
||||
mtimer: timer@200bff8 {
|
||||
compatible = "riscv,machine-timer";
|
||||
interrupts-extended = <&cpu0_intc 7>;
|
||||
reg = <0x200bff8 0x8 0x2004000 0x8>;
|
||||
reg-names = "mtime", "mtimecmp";
|
||||
};
|
||||
|
||||
uart0: serial@10000000{
|
||||
compatible = "ns16550", "snps,dw-apb-uart";
|
||||
reg = <0x10000000 0x400>;
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ Nucleo F030R8 provides the following hardware components:
|
|||
- Arduino* Uno V3 connectivity
|
||||
- ST morpho extension pin headers for full access to all STM32 I/Os
|
||||
|
||||
- ARM* mbed*
|
||||
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
|
||||
|
||||
- Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
|
||||
|
|
@ -49,6 +50,11 @@ Nucleo F030R8 provides the following hardware components:
|
|||
- Mass storage
|
||||
- Debug port
|
||||
|
||||
- Support of wide choice of Integrated Development Environments (IDEs) including:
|
||||
|
||||
- IAR
|
||||
- ARM Keil
|
||||
- GCC-based IDEs
|
||||
|
||||
More information about STM32F030R8 can be found here:
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ Nucleo F070RB provides the following hardware components:
|
|||
- Arduino* Uno V3 connectivity
|
||||
- ST morpho extension pin headers for full access to all STM32 I/Os
|
||||
|
||||
- ARM* mbed*
|
||||
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
|
||||
|
||||
- Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
|
||||
|
|
@ -49,6 +50,11 @@ Nucleo F070RB provides the following hardware components:
|
|||
- Mass storage
|
||||
- Debug port
|
||||
|
||||
- Support of wide choice of Integrated Development Environments (IDEs) including:
|
||||
|
||||
- IAR
|
||||
- ARM Keil
|
||||
- GCC-based IDEs
|
||||
|
||||
More information about STM32F070RB can be found in
|
||||
the `STM32F070 reference manual`_ .
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ Nucleo F091RC provides the following hardware components:
|
|||
- Arduino* Uno V3 connectivity
|
||||
- ST morpho extension pin headers for full access to all STM32 I/Os
|
||||
|
||||
- ARM* mbed*
|
||||
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
|
||||
|
||||
- Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
|
||||
|
|
@ -49,6 +50,11 @@ Nucleo F091RC provides the following hardware components:
|
|||
- Mass storage
|
||||
- Debug port
|
||||
|
||||
- Support of wide choice of Integrated Development Environments (IDEs) including:
|
||||
|
||||
- IAR
|
||||
- ARM Keil
|
||||
- GCC-based IDEs
|
||||
|
||||
More information about STM32F091RC can be found in the
|
||||
`STM32F091 reference manual`_
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ Nucleo F103RB provides the following hardware components:
|
|||
- Arduino* Uno V3 connectivity
|
||||
- ST morpho extension pin headers for full access to all STM32 I/Os
|
||||
|
||||
- ARM* mbed*
|
||||
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
|
||||
|
||||
- Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
|
||||
|
|
@ -49,6 +50,11 @@ Nucleo F103RB provides the following hardware components:
|
|||
- Mass storage
|
||||
- Debug port
|
||||
|
||||
- Support of wide choice of Integrated Development Environments (IDEs) including:
|
||||
|
||||
- IAR
|
||||
- ARM Keil
|
||||
- GCC-based IDEs
|
||||
|
||||
More information about STM32F103RB can be found here:
|
||||
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ Nucleo F334R8 provides the following hardware components:
|
|||
- Arduino* Uno V3 connectivity
|
||||
- ST morpho extension pin headers for full access to all STM32 I/Os
|
||||
|
||||
- ARM* mbed*
|
||||
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
|
||||
|
||||
- Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
|
||||
|
|
@ -50,6 +51,11 @@ Nucleo F334R8 provides the following hardware components:
|
|||
- Mass storage
|
||||
- Debug port
|
||||
|
||||
- Support of wide choice of Integrated Development Environments (IDEs) including:
|
||||
|
||||
- IAR
|
||||
- ARM Keil
|
||||
- GCC-based IDEs
|
||||
|
||||
More information about STM32F334R8 can be found in the
|
||||
`STM32F334 reference manual`_
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ Nucleo G070RB provides the following hardware components:
|
|||
- Arduino* Uno V3 connectivity
|
||||
- ST morpho extension pin headers for full access to all STM32 I/Os
|
||||
|
||||
- ARM* mbed*
|
||||
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
|
||||
|
||||
- Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
|
||||
|
|
@ -53,6 +54,11 @@ Nucleo G070RB provides the following hardware components:
|
|||
- Mass storage
|
||||
- Debug port
|
||||
|
||||
- Support of wide choice of Integrated Development Environments (IDEs) including:
|
||||
|
||||
- IAR
|
||||
- ARM Keil
|
||||
- GCC-based IDEs
|
||||
|
||||
More information about STM32G070RB can be found here:
|
||||
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ Nucleo G071RB provides the following hardware components:
|
|||
- Arduino* Uno V3 connectivity
|
||||
- ST morpho extension pin headers for full access to all STM32 I/Os
|
||||
|
||||
- ARM* mbed*
|
||||
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
|
||||
|
||||
- Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
|
||||
|
|
@ -53,6 +54,11 @@ Nucleo G071RB provides the following hardware components:
|
|||
- Mass storage
|
||||
- Debug port
|
||||
|
||||
- Support of wide choice of Integrated Development Environments (IDEs) including:
|
||||
|
||||
- IAR
|
||||
- ARM Keil
|
||||
- GCC-based IDEs
|
||||
|
||||
More information about STM32G071RB can be found here:
|
||||
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ Nucleo L011K4 provides the following hardware components:
|
|||
|
||||
- Arduino* Nano V3 connectivity
|
||||
|
||||
- ARM* mbed*
|
||||
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
|
||||
|
||||
- Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
|
||||
|
|
@ -48,6 +49,11 @@ Nucleo L011K4 provides the following hardware components:
|
|||
- Mass storage
|
||||
- Debug port
|
||||
|
||||
- Support of wide choice of Integrated Development Environments (IDEs) including:
|
||||
|
||||
- IAR
|
||||
- ARM Keil
|
||||
- GCC-based IDEs
|
||||
|
||||
More information about STM32L011K4 can be found in the
|
||||
`STM32L0x1 reference manual`_
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ Nucleo L053R8 provides the following hardware components:
|
|||
- Arduino* Uno V3 connectivity
|
||||
- ST morpho extension pin headers for full access to all STM32 I/Os
|
||||
|
||||
- ARM* mbed*
|
||||
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
|
||||
|
||||
- Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
|
||||
|
|
@ -49,6 +50,11 @@ Nucleo L053R8 provides the following hardware components:
|
|||
- Mass storage
|
||||
- Debug port
|
||||
|
||||
- Support of wide choice of Integrated Development Environments (IDEs) including:
|
||||
|
||||
- IAR
|
||||
- ARM Keil
|
||||
- GCC-based IDEs
|
||||
|
||||
More information about STM32L053R8 can be found in the
|
||||
`STM32L0x3 reference manual`_
|
||||
|
|
|
|||
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