f519dd1411
Use generic hook infrastrucutre instead of custom Kconfig and hooks for ARM. Replace z_arm_platform_init() with platform_reset(). Signed-off-by: Anas Nashif <anas.nashif@intel.com>
268 lines
6.5 KiB
C
268 lines
6.5 KiB
C
/*
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* Copyright (c) 2021 Argentum Systems Ltd.
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* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Atmel SAML MCU series initialization code
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <soc.h>
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#include <cmsis_core.h>
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/* the SAML21 currently operates only in Performance Level 2... sleep
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* and low-power operation are not currently supported by the BSP
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*
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* the CPU clock will be configured to 48 MHz, and run via DFLL48M.
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*
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* Reference -> GCLK Gen 1 -> DFLL48M -> GCLK Gen 0 -> GCLK_MAIN
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*
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* GCLK Gen 0 -> GCLK_MAIN @ 48 Mhz
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* GCLK Gen 1 -> DFLL48M (variable)
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* GCLK Gen 2 -> USB @ 48 MHz
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* GCLK Gen 3 -> ADC @ 24 MHz (further /2 in the ADC peripheral)
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*/
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static inline void gclk_reset(void)
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{
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/* by default, OSC16M will be enabled at 4 MHz, and the CPU will
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* run from it. to permit initialization, the CPU is temporarily
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* clocked from OSCULP32K, and OSC16M is disabled
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*/
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GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K_Val;
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OSCCTRL->OSC16MCTRL.bit.ENABLE = 0;
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}
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#if !CONFIG_SOC_ATMEL_SAML_OSC32K
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#define osc32k_init()
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#else
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static inline void osc32k_init(void)
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{
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uint32_t cal;
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/* OSC32KCAL is in NVMCTRL_OTP5[12:6] */
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cal = *((uint32_t *)NVMCTRL_OTP5);
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cal >>= 6;
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cal &= (1 << 7) - 1;
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OSC32KCTRL->OSC32K.reg = 0
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| OSC32KCTRL_OSC32K_CALIB(cal)
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| OSC32KCTRL_OSC32K_STARTUP(0x5) /* 34 cycles / ~1.038ms */
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| !OSC32KCTRL_OSC32K_ONDEMAND
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| OSC32KCTRL_OSC32K_RUNSTDBY
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| OSC32KCTRL_OSC32K_EN32K
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| OSC32KCTRL_OSC32K_ENABLE;
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/* wait for ready */
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while (!OSC32KCTRL->STATUS.bit.OSC32KRDY) {
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}
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}
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#endif
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#if !CONFIG_SOC_ATMEL_SAML_XOSC32K
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#define xosc32k_init()
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#else
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static inline void xosc32k_init(void)
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{
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OSC32KCTRL->XOSC32K.reg = 0
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| OSC32KCTRL_XOSC32K_STARTUP(0x1) /* 4096 cycles / ~0.13s */
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| !OSC32KCTRL_XOSC32K_ONDEMAND
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| OSC32KCTRL_XOSC32K_RUNSTDBY
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| OSC32KCTRL_XOSC32K_EN32K
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#if CONFIG_SOC_ATMEL_SAML_XOSC32K_CRYSTAL
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| OSC32KCTRL_XOSC32K_XTALEN
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#endif
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| OSC32KCTRL_XOSC32K_ENABLE;
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/* wait for ready */
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while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {
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}
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}
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#endif
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#if !CONFIG_SOC_ATMEL_SAML_OSC16M
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#define osc16m_init()
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#else
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static inline void osc16m_init(void)
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{
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OSCCTRL->OSC16MCTRL.reg = 0
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| !OSCCTRL_OSC16MCTRL_ONDEMAND
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| OSCCTRL_OSC16MCTRL_RUNSTDBY
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| OSCCTRL_OSC16MCTRL_FSEL_16
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| OSCCTRL_OSC16MCTRL_ENABLE;
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/* wait for ready */
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while (!OSCCTRL->STATUS.bit.OSC16MRDY) {
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}
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}
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#endif
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/* TODO: use CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC ?? */
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static inline void dfll48m_init(void)
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{
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uint32_t cal;
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/* setup the reference clock (if any) */
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GCLK->GENCTRL[1].reg = 0
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#if CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN
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| GCLK_GENCTRL_SRC_OSC32K
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#elif CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN
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| GCLK_GENCTRL_SRC_XOSC32K
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#elif CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN
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/* configure Fout = Fin / 2^(DIV+1) = 31.25 kHz
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* Fgclk_dfll48m_ref max is 33 kHz
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*/
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| GCLK_GENCTRL_DIV(8)
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| GCLK_GENCTRL_DIVSEL
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| GCLK_GENCTRL_SRC_OSC16M
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#endif
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#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
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| GCLK_GENCTRL_RUNSTDBY
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| GCLK_GENCTRL_GENEN
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#endif
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;
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#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
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/* configure and enable the generator & peripheral channel */
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GCLK->PCHCTRL[0].reg = 0
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| GCLK_PCHCTRL_CHEN
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| GCLK_PCHCTRL_GEN_GCLK1;
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#endif
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/* --- */
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/* if the target frequency is 48 MHz, then the calibration value can be used to
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* decrease the time until the coarse lock is acquired. this is loaded from
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* NVMCTRL_OTP5[31:26]
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*/
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cal = *((uint32_t *)NVMCTRL_OTP5);
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cal >>= 26;
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cal &= (1 << 6) - 1;
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OSCCTRL->DFLLCTRL.reg = 0
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| OSCCTRL_DFLLCTRL_QLDIS
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| !OSCCTRL_DFLLCTRL_ONDEMAND
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| OSCCTRL_DFLLCTRL_RUNSTDBY
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#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
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| OSCCTRL_DFLLCTRL_MODE
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#endif
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;
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OSCCTRL->DFLLVAL.reg = 0
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| OSCCTRL_DFLLVAL_COARSE(cal)
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| OSCCTRL_DFLLVAL_FINE(512) /* use 50% */
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;
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OSCCTRL->DFLLMUL.reg = 0
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/* use 25% of maximum value for the coarse and fine step
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* ... I couldn't find details on the inner workings of the DFLL, or any
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* example values for these - I have seen others using ~50%. hopefully these
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* values will provide a good balance between startup time and overshoot
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*/
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| OSCCTRL_DFLLMUL_CSTEP(16)
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| OSCCTRL_DFLLMUL_FSTEP(256)
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#if CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN || CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN
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/* use a 32.768 kHz reference ... 48e6 / 32,768 = 1,464.843... */
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| OSCCTRL_DFLLMUL_MUL(1465)
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#elif CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN
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/* use a 16 MHz -> 31.25 kHz reference... 48e6 / 31,250 = 1,536
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* a small value can make the DFLL unstable, hence not using the
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* 16 MHz source directly
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*/
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| OSCCTRL_DFLLMUL_MUL(1536)
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#endif
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;
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/* --- */
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/* enable */
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while (!OSCCTRL->STATUS.bit.DFLLRDY) {
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}
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OSCCTRL->DFLLCTRL.bit.ENABLE = 1;
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#if !CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
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/* wait for ready... note in open loop mode, we won't get a lock */
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while (!OSCCTRL->STATUS.bit.DFLLLCKC || !OSCCTRL->STATUS.bit.DFLLLCKF) {
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}
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#endif
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}
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static inline void flash_waitstates_init(void)
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{
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/* PL2, >= 2.7v, 48MHz = 2 wait states */
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NVMCTRL->CTRLB.bit.RWS = 2;
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}
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static inline void pm_init(void)
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{
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PM->PLCFG.bit.PLDIS = 0;
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PM->PLCFG.bit.PLSEL = 2;
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}
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static inline void gclk_main_configure(void)
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{
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/* finally, switch the CPU over to run from DFLL48M */
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GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val;
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}
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#if !CONFIG_USB_DC_SAM0
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#define gclk_usb_configure()
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#else
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static inline void gclk_usb_configure(void)
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{
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GCLK->GENCTRL[2].reg = 0
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| GCLK_GENCTRL_SRC_DFLL48M
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| GCLK_GENCTRL_DIV(1)
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| GCLK_GENCTRL_GENEN;
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}
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#endif
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#if !CONFIG_ADC_SAM0
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#define gclk_adc_configure()
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#else
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static inline void gclk_adc_configure(void)
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{
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GCLK->GENCTRL[3].reg = 0
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| GCLK_GENCTRL_SRC_DFLL48M
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| GCLK_GENCTRL_DIV(2)
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| GCLK_GENCTRL_GENEN;
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}
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#endif
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#if CONFIG_SOC_ATMEL_SAML_DEBUG_PAUSE
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static inline void pause_for_debug(void)
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{
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/* for some reason, when attempting to flash / debug the target, the operations
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* will time out... I suspect this is due to clock configuration, so instead of
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* doing this immediately, we defer startup for a while to permit the debugger
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* to jump in and interrupt us. ick
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*/
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for (uint32_t i = 0; i < 10000; i += 1) {
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__asm__ volatile ("nop\n");
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}
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}
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#else
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static inline void pause_for_debug(void) {}
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#endif
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void soc_reset_hook(void)
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{
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pause_for_debug();
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gclk_reset();
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osc32k_init();
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xosc32k_init();
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osc16m_init();
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dfll48m_init();
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flash_waitstates_init();
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pm_init();
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gclk_main_configure();
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gclk_usb_configure();
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gclk_adc_configure();
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}
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