7704d4eba4
Convert power management to native drivers retaining existing functionalities. Presently only SoC reset support and power control initialization is supported, but these drivers will be extended to support power management as well. MC_ME and MC_RGM peripherals are common enough to be reused by other NXP S32 devices, whereas PMC has specific implementations for each SoC series. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
158 lines
6 KiB
C
158 lines
6 KiB
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_s32_mc_me
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#include <zephyr/kernel.h>
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#if defined(CONFIG_REBOOT)
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#include <zephyr/sys/reboot.h>
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#endif /* CONFIG_REBOOT */
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/* Control Key Register */
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#define MC_ME_CTL_KEY 0x0
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#define MC_ME_CTL_KEY_KEY_MASK GENMASK(15, 0)
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#define MC_ME_CTL_KEY_KEY(v) FIELD_PREP(MC_ME_CTL_KEY_KEY_MASK, (v))
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/* Mode Configuration Register */
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#define MC_ME_MODE_CONF 0x4
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#define MC_ME_MODE_CONF_DEST_RST_MASK BIT(0)
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#define MC_ME_MODE_CONF_DEST_RST(v) FIELD_PREP(MC_ME_MODE_CONF_DEST_RST_MASK, (v))
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#define MC_ME_MODE_CONF_FUNC_RST_MASK BIT(1)
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#define MC_ME_MODE_CONF_FUNC_RST(v) FIELD_PREP(MC_ME_MODE_CONF_FUNC_RST_MASK, (v))
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#define MC_ME_MODE_CONF_STANDBY_MASK BIT(15)
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#define MC_ME_MODE_CONF_STANDBY(v) FIELD_PREP(MC_ME_MODE_CONF_STANDBY_MASK, (v))
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/* Mode Update Register */
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#define MC_ME_MODE_UPD 0x8
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#define MC_ME_MODE_UPD_MODE_UPD_MASK BIT(0)
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#define MC_ME_MODE_UPD_MODE_UPD(v) FIELD_PREP(MC_ME_MODE_UPD_MODE_UPD_MASK, (v))
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/* Mode Status Register */
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#define MC_ME_MODE_STAT 0xc
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#define MC_ME_MODE_STAT_PREV_MODE_MASK BIT(0)
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#define MC_ME_MODE_STAT_PREV_MODE(v) FIELD_PREP(MC_ME_MODE_STAT_PREV_MODE_MASK, (v))
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/* Main Core ID Register */
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#define MC_ME_MAIN_COREID 0x10
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#define MC_ME_MAIN_COREID_CIDX_MASK GENMASK(2, 0)
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#define MC_ME_MAIN_COREID_CIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_CIDX_MASK, (v))
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#define MC_ME_MAIN_COREID_PIDX_MASK GENMASK(12, 8)
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#define MC_ME_MAIN_COREID_PIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_PIDX_MASK, (v))
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/* Partition p Process Configuration Register */
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#define MC_ME_PRTN_PCONF(p) (0x100 + 0x200 * (p))
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#define MC_ME_PRTN_PCONF_PCE_MASK BIT(0)
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#define MC_ME_PRTN_PCONF_PCE(v) FIELD_PREP(MC_ME_PRTN_PCONF_PCE_MASK, (v))
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/* Partition p Process Update Register */
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#define MC_ME_PRTN_PUPD(p) (0x104 + 0x200 * (p))
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#define MC_ME_PRTN_PUPD_PCUD_MASK BIT(0)
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#define MC_ME_PRTN_PUPD_PCUD(v) FIELD_PREP(MC_ME_PRTN_PUPD_PCUD_MASK, (v))
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/* Partition p Status Register */
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#define MC_ME_PRTN_STAT(p) (0x108 + 0x200 * (p))
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#define MC_ME_PRTN_STAT_PCS_MASK BIT(0)
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#define MC_ME_PRTN_STAT_PCS(v) FIELD_PREP(MC_ME_PRTN_STAT_PCS_MASK, (v))
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/* Partition p COFB c Clock Status Register */
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#define MC_ME_PRTN_COFB_STAT(p, c) (0x110 + 0x200 * (p) + 0x4 * (c))
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/* Partition p COFB c Clock Enable Register */
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#define MC_ME_PRTN_COFB_CLKEN(p, c) (0x130 + 0x200 * (p) + 0x4 * (c))
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/* Partition p Core c Process Configuration Register */
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#define MC_ME_PRTN_CORE_PCONF(p, c) (0x140 + 0x200 * (p) + 0x20 * (c))
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#define MC_ME_PRTN_CORE_PCONF_CCE_MASK BIT(0)
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#define MC_ME_PRTN_CORE_PCONF_CCE(v) FIELD_PREP(MC_ME_PRTN_CORE_PCONF_CCE_MASK, (v))
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/* Partition n Core c Process Update Register */
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#define MC_ME_PRTN_CORE_PUPD(p, c) (0x144 + 0x200 * (p) + 0x20 * (c))
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#define MC_ME_PRTN_CORE_PUPD_CCUPD_MASK BIT(0)
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#define MC_ME_PRTN_CORE_PUPD_CCUPD(v) FIELD_PREP(MC_ME_PRTN_CORE_PUPD_CCUPD_MASK, (v))
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/* Partition n Core c Status Register */
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#define MC_ME_PRTN_CORE_STAT(p, c) (0x148 + 0x200 * (p) + 0x20 * (c))
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#define MC_ME_PRTN_CORE_STAT_CCS_MASK BIT(0)
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#define MC_ME_PRTN_CORE_STAT_CCS(v) FIELD_PREP(MC_ME_PRTN_CORE_STAT_CCS_MASK, (v))
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#define MC_ME_PRTN_CORE_STAT_WFI_MASK BIT(31)
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#define MC_ME_PRTN_CORE_STAT_WFI(v) FIELD_PREP(MC_ME_PRTN_CORE_STAT_WFI_MASK, (v))
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/* Partition n Core c Address Register */
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#define MC_ME_PRTN_CORE_ADDR(p, c) (0x14c + 0x200 * (p) + 0x20 * (c))
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#define MC_ME_PRTN_CORE_ADDR_ADDR_MASK GENMASK(31, 2)
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#define MC_ME_PRTN_CORE_ADDR_ADDR(v) FIELD_PREP(MC_ME_PRTN_CORE_ADDR_ADDR_MASK, (v))
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#define MC_ME_CTL_KEY_DIRECT_KEY 0x00005af0U
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#define MC_ME_CTL_KEY_INVERTED_KEY 0x0000a50fU
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/* Handy accessors */
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#define REG_READ(r) sys_read32((mem_addr_t)(DT_INST_REG_ADDR(0) + (r)))
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#define REG_WRITE(r, v) sys_write32((v), (mem_addr_t)(DT_INST_REG_ADDR(0) + (r)))
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/** MC_ME power mode */
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enum mc_me_power_mode {
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/** Destructive Reset Mode */
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MC_ME_DEST_RESET_MODE,
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/** Functional Reset Mode */
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MC_ME_FUNC_RESET_MODE,
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};
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#if defined(CONFIG_REBOOT)
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static inline void mc_me_write_ctl_key(void)
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{
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REG_WRITE(MC_ME_CTL_KEY, MC_ME_CTL_KEY_KEY(MC_ME_CTL_KEY_DIRECT_KEY));
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REG_WRITE(MC_ME_CTL_KEY, MC_ME_CTL_KEY_KEY(MC_ME_CTL_KEY_INVERTED_KEY));
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}
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static inline void mc_me_trigger_mode_update(void)
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{
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REG_WRITE(MC_ME_MODE_UPD, MC_ME_MODE_UPD_MODE_UPD(1U));
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mc_me_write_ctl_key();
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}
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static int mc_me_set_mode(enum mc_me_power_mode mode)
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{
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int err = 0;
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switch (mode) {
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case MC_ME_DEST_RESET_MODE:
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REG_WRITE(MC_ME_MODE_CONF, MC_ME_MODE_CONF_DEST_RST(1U));
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mc_me_trigger_mode_update();
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break;
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case MC_ME_FUNC_RESET_MODE:
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REG_WRITE(MC_ME_MODE_CONF, MC_ME_MODE_CONF_FUNC_RST(1U));
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mc_me_trigger_mode_update();
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break;
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default:
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err = -ENOTSUP;
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break;
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}
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return err;
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}
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/*
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* Overrides default weak implementation of system reboot.
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*
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* SYS_REBOOT_COLD (Destructive Reset):
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* - Leads most parts of the chip, except a few modules, to reset. SRAM content
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* is lost after this reset event.
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* - Flash is always reset, so an updated value of the option bits is reloaded
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* in volatile registers outside of the Flash array.
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* - Trimming is lost.
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* - STCU is reset and configured BISTs are executed.
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*
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* SYS_REBOOT_WARM (Functional Reset):
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* - Leads all the communication peripherals and cores to reset. The communication
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* protocols' sanity is not guaranteed and they are assumed to be reinitialized
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* after reset. The SRAM content, and the functionality of certain modules, is
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* preserved across functional reset.
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* - The volatile registers are not reset; in case of a reset event, the
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* trimming is maintained.
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* - No BISTs are executed after functional reset.
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*/
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void sys_arch_reboot(int type)
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{
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switch (type) {
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case SYS_REBOOT_COLD:
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mc_me_set_mode(MC_ME_DEST_RESET_MODE);
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break;
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case SYS_REBOOT_WARM:
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mc_me_set_mode(MC_ME_FUNC_RESET_MODE);
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break;
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default:
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/* Do nothing */
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break;
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}
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}
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#endif /* CONFIG_REBOOT */
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