aef9bdf348
FPGA drivers should be built on a regular basis to ensure that there are no regressions. To that end, the sensors build_all test was cloned, trimmed-down, and the ice40 driver is built with the two separate devicetree-specified configurations (load modes). The first load mode is for regular SPI bitstream flashing (useful for higher-end microcontrollers with a faster clock). The second load mode is for bitbanged GPIO bitstream flashing (useful for lower-end microcontrollers that need to squeeze every cycle of performance to meet timing requirements for iCE40 bitstream loading). Signed-off-by: Chris Friedt <cfriedt@meta.com>
10 lines
259 B
CMake
10 lines
259 B
CMake
# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(build_all)
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zephyr_include_directories(src)
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FILE(GLOB app_sources src/*.c)
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target_sources(app PRIVATE ${app_sources})
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