bbe5e1e6eb
Namespaced the generated headers with `zephyr` to prevent potential conflict with other headers. Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH` that is enabled by default. This allows the developers to continue the use of the old include paths for the time being until it is deprecated and eventually removed. The Kconfig will generate a build-time warning message, similar to the `CONFIG_TIMER_RANDOM_GENERATOR`. Updated the includes path of in-tree sources accordingly. Most of the changes here are scripted, check the PR for more info. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
256 lines
5 KiB
ArmAsm
256 lines
5 KiB
ArmAsm
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/offsets.h>
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#include "boot.h"
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#include "macro_priv.inc"
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_ASM_FILE_PROLOGUE
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/*
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* Platform specific pre-C init code
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*
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* Note: - Stack is not yet available
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* - x23, x24 and x25 must be preserved
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*/
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WTEXT(z_arm64_el3_plat_prep_c)
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SECTION_FUNC(TEXT,z_arm64_el3_plat_prep_c)
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ret
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WTEXT(z_arm64_el2_plat_prep_c)
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SECTION_FUNC(TEXT,z_arm64_el2_plat_prep_c)
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ret
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WTEXT(z_arm64_el1_plat_prep_c)
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SECTION_FUNC(TEXT,z_arm64_el1_plat_prep_c)
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ret
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/*
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* Set the minimum necessary to safely call C code
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*/
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GTEXT(__reset_prep_c)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset_prep_c)
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/* return address: x23 */
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mov x23, lr
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switch_el x0, 3f, 2f, 1f
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3:
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#if !defined(CONFIG_ARMV8_R)
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/* Reinitialize SCTLR from scratch in EL3 */
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ldr w0, =(SCTLR_EL3_RES1 | SCTLR_I_BIT | SCTLR_SA_BIT)
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msr sctlr_el3, x0
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isb
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/* Custom plat prep_c init */
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bl z_arm64_el3_plat_prep_c
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/* Set SP_EL1 */
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msr sp_el1, x24
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b out
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#endif /* CONFIG_ARMV8_R */
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2:
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/* Disable alignment fault checking */
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mrs x0, sctlr_el2
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bic x0, x0, SCTLR_A_BIT
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msr sctlr_el2, x0
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isb
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/* Custom plat prep_c init */
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bl z_arm64_el2_plat_prep_c
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/* Set SP_EL1 */
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msr sp_el1, x24
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b out
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1:
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/* Disable alignment fault checking */
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mrs x0, sctlr_el1
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bic x0, x0, SCTLR_A_BIT
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msr sctlr_el1, x0
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isb
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/* Custom plat prep_c init */
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bl z_arm64_el1_plat_prep_c
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/* Set SP_EL1. We cannot use sp_el1 at EL1 */
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msr SPSel, #1
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mov sp, x24
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out:
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isb
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/* Select SP_EL0 */
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msr SPSel, #0
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/* Initialize stack */
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mov sp, x24
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/* fp = NULL */
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mov fp, xzr
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ret x23
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/*
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* Reset vector
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*
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* Ran when the system comes out of reset. The processor is in thread mode with
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* privileged level. At this point, neither SP_EL0 nor SP_ELx point to a valid
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* area in SRAM.
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*/
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GTEXT(__reset)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset)
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GTEXT(__start)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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#ifdef CONFIG_WAIT_AT_RESET_VECTOR
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resetwait:
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wfe
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b resetwait
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#endif
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/* Mask all exceptions */
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msr DAIFSet, #0xf
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#if CONFIG_MP_MAX_NUM_CPUS > 1
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/*
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* Deal with multi core booting simultaneously to race for being the primary core.
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* Use voting lock[1] with reasonable but minimal requirements on the memory system
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* to make sure only one core wins at last.
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*
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* [1] kernel.org/doc/html/next/arch/arm/vlocks.html
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*/
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ldr x0, =arm64_cpu_boot_params
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/*
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* Get the "logic" id defined by cpu_node_list statically for voting lock self-identify.
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* It is worth noting that this is NOT the final logic id (arch_curr_cpu()->id)
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*/
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get_cpu_logic_id x1, x2, x3, x4 //x1: MPID, x2: logic id
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add x4, x0, #BOOT_PARAM_VOTING_OFFSET
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/* signal our desire to vote */
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mov w5, #1
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strb w5, [x4, x2]
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ldr x3, [x0, #BOOT_PARAM_MPID_OFFSET]
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cmn x3, #1
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beq 1f
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/* some core already won, release */
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strb wzr, [x4, x2]
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b secondary_core
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/* suggest current core then release */
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1: str x1, [x0, #BOOT_PARAM_MPID_OFFSET]
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strb wzr, [x4, x2]
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dmb ish
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/* then wait until every core else is done voting */
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mov x5, #0
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2: ldrb w3, [x4, x5]
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tst w3, #255
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/* wait */
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bne 2b
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add x5, x5, #1
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cmp x5, #CONFIG_MP_MAX_NUM_CPUS
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bne 2b
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/* check if current core won */
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dmb ish
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ldr x3, [x0, #BOOT_PARAM_MPID_OFFSET]
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cmp x3, x1
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beq primary_core
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/* fallthrough secondary */
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/* loop until our turn comes */
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secondary_core:
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dmb ish
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ldr x2, [x0, #BOOT_PARAM_MPID_OFFSET]
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cmp x1, x2
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bne secondary_core
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/* we can now load our stack pointer value and move on */
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ldr x24, [x0, #BOOT_PARAM_SP_OFFSET]
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ldr x25, =z_arm64_secondary_prep_c
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b boot
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primary_core:
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#endif
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/* load primary stack and entry point */
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ldr x24, =(z_interrupt_stacks + __z_interrupt_stack_SIZEOF)
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ldr x25, =z_prep_c
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boot:
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/* Prepare for calling C code */
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bl __reset_prep_c
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/*
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* Initialize the interrupt stack with 0xaa so stack utilization
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* can be measured. This needs to be done before using the stack
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* so that we don't clobber any data.
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*/
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#ifdef CONFIG_INIT_STACKS
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mov_imm x0, CONFIG_ISR_STACK_SIZE
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sub x0, sp, x0
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sub x9, sp, #8
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mov x10, 0xaaaaaaaaaaaaaaaa
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stack_init_loop:
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cmp x0, x9
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beq stack_init_done
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str x10, [x0], #8
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b stack_init_loop
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stack_init_done:
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#endif
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/* Platform hook for highest EL */
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bl z_arm64_el_highest_init
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switch_el:
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switch_el x0, 3f, 2f, 1f
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3:
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#if !defined(CONFIG_ARMV8_R)
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/* EL3 init */
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bl z_arm64_el3_init
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/* Get next EL */
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adr x0, switch_el
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bl z_arm64_el3_get_next_el
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eret
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#endif /* CONFIG_ARMV8_R */
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2:
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/* EL2 init */
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bl z_arm64_el2_init
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/* Move to EL1 with all exceptions masked */
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mov_imm x0, (SPSR_DAIF_MASK | SPSR_MODE_EL1T)
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msr spsr_el2, x0
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adr x0, 1f
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msr elr_el2, x0
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eret
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1:
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/* EL1 init */
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bl z_arm64_el1_init
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/* We want to use SP_ELx from now on */
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msr SPSel, #1
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/* Enable SError interrupts */
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msr DAIFClr, #(DAIFCLR_ABT_BIT)
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isb
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ret x25 /* either z_prep_c or z_arm64_secondary_prep_c */
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