588ccd9698
`CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` had been deprecated since #66877 for 2 releases, interrupt controller drivers should have been updated to use the new `IRQ_PARENT_ENTRY_DEFINE()` macro. Remove it. Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
68 lines
3.1 KiB
Text
68 lines
3.1 KiB
Text
# Common architecture configuration options
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# Copyright (c) 2022, CSIRO.
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# SPDX-License-Identifier: Apache-2.0
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config SEMIHOST
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bool "Semihosting support for ARM and RISC-V targets"
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depends on ARM || ARM64 || RISCV
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help
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Semihosting is a mechanism that enables code running on an ARM or
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RISC-V target to communicate and use the Input/Output facilities on
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a host computer that is running a debugger.
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Additional information can be found in:
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https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
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https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
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This option is compatible with hardware and with QEMU, through the
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(automatic) use of the -semihosting-config switch when invoking it.
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config ISR_TABLE_SHELL
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bool "Shell command to dump the ISR tables"
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depends on GEN_SW_ISR_TABLE
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depends on SHELL
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help
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This option enables a shell command to dump the ISR tables.
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config ARM_MPU
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bool "ARM MPU Support"
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select MPU
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select SRAM_REGION_PERMISSIONS
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select THREAD_STACK_INFO
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select ARCH_HAS_EXECUTABLE_PAGE_BIT if (CPU_AARCH32_CORTEX_R || CPU_CORTEX_M)
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select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_SYSMPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
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select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if CPU_HAS_ARM_MPU && (ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
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select MPU_GAP_FILLING if AARCH32_ARMV8_R
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select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS if (CPU_AARCH32_CORTEX_R || CPU_CORTEX_M)
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select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE && CPU_AARCH64_CORTEX_R
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default y if CPU_AARCH64_CORTEX_R
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depends on CPU_HAS_MPU
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help
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MCU implements Memory Protection Unit.
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Notes:
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The ARMv6-M, ARMv7-M, and ARMv8-R MPU MPU architecture requires a power-of-two
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alignment of MPU region base address and size.
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The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
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to have power-of-two alignment for base address and region size.
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The ARMv8-M and ARMv8-R MPU requires the active MPU regions be non-overlapping.
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As a result of this, both respective MPUs needs to fully partition the
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memory map when programming dynamic memory regions (e.g. PRIV stack
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guard, user thread stack, and application memory domains), if the
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system requires PRIV access policy different from the access policy
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of the ARMv8-M or ARMv8-R background memory map. The application developer may
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enforce full PRIV (kernel) memory partition by enabling the
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MPU_GAP_FILLING option.
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By not enforcing full partition, MPU may leave part of kernel
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SRAM area covered only by the default ARMv8-M or ARMv8-R memory map. This
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is fine for User Mode, since the background ARM map does not
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allow nPRIV access at all. However, since the background map
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policy allows instruction fetches by privileged code, forcing
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this Kconfig option off prevents the system from directly
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triggering MemManage exceptions upon accidental attempts to
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execute code from SRAM in XIP builds.
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Since this does not compromise User Mode, we make the skipping
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of full partitioning the default behavior for the ARMv8-M and ARMv8-R MPU
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driver.
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