2803dcd564
Remove the limitation of number of cpu support in x86 arch. Also add support for retrieve cpu informations such as for hybird cores. Signed-off-by: Najumon B.A <najumon.ba@intel.com>
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
/*
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* Copyright (c) 2019 Intel Corp.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ARCH_X86_INCLUDE_INTEL64_KERNEL_ARCH_DATA_H_
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#define ZEPHYR_ARCH_X86_INCLUDE_INTEL64_KERNEL_ARCH_DATA_H_
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#include <zephyr/arch/x86/mmustructs.h>
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#ifndef _ASMLANGUAGE
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/* linker symbols defining the bounds of the kernel part loaded in locore */
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extern char _locore_start[], _locore_end[];
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/*
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* Per-CPU bootstrapping parameters. See locore.S and cpu.c.
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*/
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struct x86_cpuboot {
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volatile int ready; /* CPU has started */
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uint16_t tr; /* selector for task register */
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struct x86_tss64 *gs_base; /* Base address for GS segment */
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uint64_t sp; /* initial stack pointer */
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size_t stack_size; /* size of stack */
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arch_cpustart_t fn; /* kernel entry function */
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void *arg; /* argument for above function */
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uint8_t cpu_id; /* CPU ID */
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};
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typedef struct x86_cpuboot x86_cpuboot_t;
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extern uint8_t x86_cpu_loapics[]; /* CPU logical ID -> local APIC ID */
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#endif /* _ASMLANGUAGE */
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#ifdef CONFIG_X86_KPTI
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#define Z_X86_TRAMPOLINE_STACK_SIZE 128
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#endif
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#ifdef CONFIG_X86_KPTI
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#define TRAMPOLINE_STACK(n) \
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uint8_t z_x86_trampoline_stack##n[Z_X86_TRAMPOLINE_STACK_SIZE] \
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__attribute__ ((section(".trampolines")));
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#define TRAMPOLINE_INIT(n) \
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.ist2 = (uint64_t)z_x86_trampoline_stack##n + Z_X86_TRAMPOLINE_STACK_SIZE,
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#else
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#define TRAMPOLINE_STACK(n)
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#define TRAMPOLINE_INIT(n)
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#endif /* CONFIG_X86_KPTI */
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#define ACPI_CPU_INIT(n, _) \
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uint8_t z_x86_exception_stack##n[CONFIG_X86_EXCEPTION_STACK_SIZE] __aligned(16); \
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uint8_t z_x86_nmi_stack##n[CONFIG_X86_EXCEPTION_STACK_SIZE] __aligned(16); \
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TRAMPOLINE_STACK(n); \
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Z_GENERIC_SECTION(.tss) \
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struct x86_tss64 tss##n = { \
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TRAMPOLINE_INIT(n) \
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.ist6 = (uint64_t)z_x86_nmi_stack##n + CONFIG_X86_EXCEPTION_STACK_SIZE, \
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.ist7 = (uint64_t)z_x86_exception_stack##n + CONFIG_X86_EXCEPTION_STACK_SIZE, \
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.iomapb = 0xFFFF, .cpu = &(_kernel.cpus[n]) \
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}
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#define X86_CPU_BOOT_INIT(n, _) \
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{ \
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.tr = (0x40 + (16 * n)), \
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.gs_base = &tss##n, \
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.sp = (uint64_t)z_interrupt_stacks[n] + \
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K_KERNEL_STACK_LEN(CONFIG_ISR_STACK_SIZE), \
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.stack_size = K_KERNEL_STACK_LEN(CONFIG_ISR_STACK_SIZE), \
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.fn = z_prep_c, \
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.arg = &x86_cpu_boot_arg, \
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}
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#define STACK_ARRAY_IDX(n, _) n
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#define DEFINE_STACK_ARRAY_IDX\
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LISTIFY(CONFIG_MP_MAX_NUM_CPUS, STACK_ARRAY_IDX, (,))
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#endif /* ZEPHYR_ARCH_X86_INCLUDE_INTEL64_KERNEL_ARCH_DATA_H_ */
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