2363b6b595
Add a DTS binding for the MediaTek Audio Front End device, and definitions for the in-tree devices. These .dts files were auto-generated from pre-existing SOF code (that defined the devices as C structs) using a tool currently being submitted in the SOF tree, thus are included here as separate files. The expectation is that future variants will be authored in this format directly. Longer term we can move them directly into the core board DTS. Signed-off-by: Andy Ross <andyross@google.com>
113 lines
2.7 KiB
Text
113 lines
2.7 KiB
Text
/* Copyright 2024 The ChromiumOS Authors
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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sram0: memory@4e100000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x4e100000 DT_SIZE_K(512)>;
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};
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dram0: memory@90000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x90000000 DT_SIZE_M(6)>;
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};
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dram1: memory@90800000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x90800000 DT_SIZE_M(1)>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0 4>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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/* The 8196 interrupt controller is actually more complicated
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* than the driver here supports. There are 64 total
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* interrupt inputs, each of which is a associated with one of
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* 16 "groups", each of which is wired to a separate Xtensa
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* architectural interrupt. (Whether the mapping of external
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* interrupts to groups is mutable is an open question, the
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* values here appear to be hardware defaults). We represent
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* each group (strictly each of the high and low 32 interrupts
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* of each group) as a separate adsp_intc controller, pointing
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* at the same status and enable registers, but with disjoint
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* masks. Note that this disallows configurations where a
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* single controller needs to manage interrupts in both the
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* high and low 32 bits of the set, but no current drivers
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* rely on such a configuration.
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*/
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intc_g1: intc_g1@1a014010 {
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compatible = "mediatek,adsp_intc";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1a014010 4>;
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status-reg = <0x1a014008>;
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mask = <0x00007f3f>;
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interrupts = <1 0 0>;
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interrupt-parent = <&core_intc>;
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};
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intc_g2: intc_g2@1a014010 {
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compatible = "mediatek,adsp_intc";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1a014010 4>;
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status-reg = <0x1a014008>;
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mask = <0x000000c0>;
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interrupts = <2 0 0>;
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interrupt-parent = <&core_intc>;
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};
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ostimer64: ostimer64@1a00b080 {
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compatible = "mediatek,ostimer64";
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reg = <0x1a00b080 28>;
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};
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ostimer0: ostimer@1a00b000 {
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compatible = "mediatek,ostimer";
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reg = <0x1a00b000 16>;
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interrupt-parent = <&intc_g1>;
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interrupts = <8 0 0>;
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};
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mbox0: mbox@1a350100 {
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compatible = "mediatek,mbox";
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reg = <0x1a350100 16>;
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interrupt-parent = <&intc_g2>;
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interrupts = <6 0 0>;
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};
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mbox1: mbox@1a360100 {
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compatible = "mediatek,mbox";
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reg = <0x1a360100 16>;
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interrupt-parent = <&intc_g2>;
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interrupts = <7 0 0>;
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};
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/* Generated code for AFE devices */
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#include "afe-mt8196.dts"
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}; /* soc */
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chosen { };
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aliases { };
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};
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