33f905009d
Add link to eSPI spec 1.5 Update coding guidelines for eSPI bus Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
27 lines
884 B
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27 lines
884 B
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.. _espi_api:
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Enhanced Serial Peripheral Interface (eSPI) Bus
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###############################################
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Overview
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The eSPI (enhanced serial peripheral interface) is a serial bus that is
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based on SPI. It also features a four-wire interface (receive, transmit, clock
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and target select) and three configurations: single IO, dual IO and quad IO.
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The technical advancements include lower voltage signal levels (1.8V vs. 3.3V),
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lower pin count, and the frequency is twice as fast (66MHz vs. 33MHz)
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Because of its enhancements, the eSPI is used to replace the LPC
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(lower pin count) interface, SPI, SMBus and sideband signals.
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See `eSPI interface specification`_ for additional details.
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API Reference
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*************
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.. doxygengroup:: espi_interface
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.. _eSPI interface specification:
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https://downloadmirror.intel.com/27055/327432%20espi_base_specification%20R1-5.pdf
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