cbaafe209c
The nRF54 and nRF92 chips has data cache, which means the ICMsg and ICBMsg must be configured to follow required cache alignment of the shared memory. The `dcache-alignement` needs to be defined for that. Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no> |
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| .. | ||
| icbmsg_flows.svg | ||
| icbmsg_memory.svg | ||
| icbmsg_message.svg | ||
| ipc_service_icbmsg.rst | ||
| ipc_service_icmsg.rst | ||
