cbf867ff2c
We add a serial UART driver for Microchip MEC5 HAL based chips. The driver supports polling, interrupts, and runtime configuration features. Power management will be implemented in a future PR. Signed-off-by: Scott Worley <scott.worley@microchip.com>
662 lines
18 KiB
C
662 lines
18 KiB
C
/*
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* Copyright (c) 2024 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Microchip MEC5 ns16550 compatible UART Serial Driver
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*/
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#define DT_DRV_COMPAT microchip_mec5_uart
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#include <errno.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/sys/byteorder.h>
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LOG_MODULE_REGISTER(uart_mec5, CONFIG_UART_LOG_LEVEL);
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/* MEC5 HAL */
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#include <device_mec5.h>
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#include <mec_ecia_api.h>
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#include <mec_uart_api.h>
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#define UART_MEC_DFLT_CLK_FREQ 1843200u
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#define UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_POS 0
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#define UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_MSK 0x3u
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#define UART_MEC_DEVCFG_FLAG_FIFO_DIS_POS 4
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#define UART_MEC_DEVCFG_FLAG_USE_EXTCLK_POS 5
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struct uart_mec5_devcfg {
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struct mec_uart_regs *regs;
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const struct pinctrl_dev_config *pcfg;
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uint32_t clock_freq;
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uint32_t flags;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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void (*irq_config_func)(const struct device *dev);
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#endif
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};
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struct uart_mec5_dev_data {
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const struct device *dev;
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struct uart_config current_config;
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struct uart_config ucfg;
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struct k_spinlock lock;
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enum mec_uart_ipend ipend;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t cb; /* Callback function pointer */
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void *cb_data; /* Callback function arg */
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uint32_t flags;
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uint8_t rx_enabled;
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uint8_t tx_enabled;
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#endif
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};
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static const uint8_t mec5_xlat_word_len[4] = {
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MEC_UART_WORD_LEN_5,
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MEC_UART_WORD_LEN_6,
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MEC_UART_WORD_LEN_7,
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MEC_UART_WORD_LEN_8,
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};
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static const uint8_t mec5_xlat_stop_bits[4] = {
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MEC_UART_STOP_BITS_1,
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MEC_UART_STOP_BITS_1,
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MEC_UART_STOP_BITS_2,
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MEC_UART_STOP_BITS_2,
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};
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static const uint8_t mec5_xlat_parity[5] = {
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(uint8_t)(MEC5_UART_CFG_PARITY_NONE >> MEC5_UART_CFG_PARITY_POS),
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(uint8_t)(MEC5_UART_CFG_PARITY_ODD >> MEC5_UART_CFG_PARITY_POS),
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(uint8_t)(MEC5_UART_CFG_PARITY_EVEN >> MEC5_UART_CFG_PARITY_POS),
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(uint8_t)(MEC5_UART_CFG_PARITY_MARK >> MEC5_UART_CFG_PARITY_POS),
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(uint8_t)(MEC5_UART_CFG_PARITY_SPACE >> MEC5_UART_CFG_PARITY_POS),
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};
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static int uart_mec5_xlat_cfg(const struct uart_config *cfg, uint32_t *cfg_word)
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{
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uint32_t temp;
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if (!cfg || !cfg_word) {
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return -EINVAL;
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}
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*cfg_word = 0u;
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if (cfg->data_bits > UART_CFG_DATA_BITS_8) {
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return -EINVAL;
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}
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temp = mec5_xlat_word_len[cfg->data_bits];
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*cfg_word |= ((temp << MEC5_UART_CFG_WORD_LEN_POS) & MEC5_UART_CFG_WORD_LEN_MSK);
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if (cfg->stop_bits > UART_CFG_STOP_BITS_2) {
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return -EINVAL;
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}
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temp = mec5_xlat_stop_bits[cfg->stop_bits];
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*cfg_word |= ((temp << MEC5_UART_CFG_STOP_BITS_POS) & MEC5_UART_CFG_STOP_BITS_MSK);
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if (cfg->parity > UART_CFG_PARITY_SPACE) {
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return -EINVAL;
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}
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temp = mec5_xlat_parity[cfg->parity];
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*cfg_word |= ((temp << MEC5_UART_CFG_PARITY_POS) & MEC5_UART_CFG_PARITY_MSK);
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return 0;
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}
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/* Configure UART TX and RX FIFOs based on device tree.
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* Both FIFOs are fixed 16-byte.
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* RX FIFO has a configurable interrupt trigger level of 1, 4, 8, or 14 bytes.
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*/
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static uint32_t uart_mec5_fifo_config(uint32_t mcfg, uint32_t cfg_flags)
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{
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uint32_t new_mcfg = mcfg;
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uint32_t temp = 0;
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if (!(cfg_flags & BIT(UART_MEC_DEVCFG_FLAG_FIFO_DIS_POS))) {
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new_mcfg |= BIT(MEC5_UART_CFG_FIFO_EN_POS);
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temp = (cfg_flags & UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_MSK) >>
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UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_POS;
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switch (temp) {
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case 0:
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new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_1;
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break;
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case 1:
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new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_4;
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break;
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case 2:
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new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_8;
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break;
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default:
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new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_14;
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break;
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}
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}
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return new_mcfg;
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}
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static int config_mec5_uart(const struct device *dev, const struct uart_config *cfg)
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{
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const struct uart_mec5_devcfg *devcfg = dev->config;
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struct mec_uart_regs *const regs = devcfg->regs;
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struct uart_mec5_dev_data *const data = dev->data;
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int ret = 0;
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uint32_t mcfg = 0, extclk = 0;
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data->ipend = MEC_UART_IPEND_NONE;
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ret = uart_mec5_xlat_cfg(cfg, &mcfg);
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if (ret) {
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return ret;
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}
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mcfg = uart_mec5_fifo_config(mcfg, devcfg->flags);
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mcfg |= BIT(MEC5_UART_CFG_GIRQ_EN_POS);
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if (devcfg->flags & BIT(UART_MEC_DEVCFG_FLAG_USE_EXTCLK_POS)) {
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extclk = devcfg->clock_freq;
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}
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ret = mec_hal_uart_init(regs, cfg->baudrate, mcfg, extclk);
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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memcpy(&data->ucfg, cfg, sizeof(struct uart_config));
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return ret;
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};
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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/* run-time driver configuration API */
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static int uart_mec5_configure(const struct device *dev, const struct uart_config *cfg)
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{
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const struct uart_mec5_devcfg *devcfg = dev->config;
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struct uart_mec5_dev_data *const data = dev->data;
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int ret = 0;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret) {
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LOG_ERR("MEC5 UART pinctrl error (%d)", ret);
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}
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ret = config_mec5_uart(dev, cfg);
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if (ret) {
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LOG_ERR("MEC5 UART config error (%d)", ret);
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return ret;
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}
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data->current_config = *cfg;
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k_spin_unlock(&data->lock, key);
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return ret;
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}
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static int uart_mec5_config_get(const struct device *dev, struct uart_config *cfg)
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{
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struct uart_mec5_dev_data *const data = dev->data;
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if (!cfg) {
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return -EINVAL;
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}
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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*cfg = data->current_config;
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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/* Called by kernel during driver initialization phase */
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static int uart_mec5_init(const struct device *dev)
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{
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const struct uart_mec5_devcfg *devcfg = dev->config;
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struct uart_mec5_dev_data *data = dev->data;
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int ret = 0;
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ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret) {
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LOG_ERR("MEC5 UART init pinctrl error (%d)", ret);
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return ret;
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}
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ret = config_mec5_uart(dev, &data->ucfg);
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if (ret != 0) {
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return -EIO;
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}
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return ret;
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}
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/*
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* Poll the UART for input.
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* return 0 is a byte arrived else -1 if no data.
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*/
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static int uart_mec5_poll_in(const struct device *dev, unsigned char *cptr)
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{
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const struct uart_mec5_devcfg *devcfg = dev->config;
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struct mec_uart_regs *const regs = devcfg->regs;
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struct uart_mec5_dev_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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int ret = 0;
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ret = mec_hal_uart_rx_byte(regs, (uint8_t *)cptr);
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if (ret == MEC_RET_ERR_NO_DATA) {
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k_spin_unlock(&data->lock, key);
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return -1;
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}
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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/* Block until UART can accept data byte. */
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static void uart_mec5_poll_out(const struct device *dev, unsigned char out_data)
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{
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const struct uart_mec5_devcfg *devcfg = dev->config;
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struct mec_uart_regs *const regs = devcfg->regs;
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struct uart_mec5_dev_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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int ret = 0;
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do {
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ret = mec_hal_uart_tx_byte(regs, (uint8_t)out_data);
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} while (ret == MEC_RET_ERR_BUSY);
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k_spin_unlock(&data->lock, key);
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static inline void irq_tx_enable(const struct device *dev)
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{
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const struct uart_mec5_devcfg *devcfg = dev->config;
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struct mec_uart_regs *const regs = devcfg->regs;
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struct uart_mec5_dev_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ETHREI, MEC_UART_IEN_FLAG_ETHREI);
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k_spin_unlock(&data->lock, key);
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}
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static inline void irq_tx_disable(const struct device *dev)
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{
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const struct uart_mec5_devcfg *devcfg = dev->config;
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struct uart_mec5_dev_data *data = dev->data;
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struct mec_uart_regs *const regs = devcfg->regs;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ETHREI, 0);
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k_spin_unlock(&data->lock, key);
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}
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static inline void irq_rx_enable(const struct device *dev)
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{
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const struct uart_mec5_devcfg *const devcfg = dev->config;
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struct uart_mec5_dev_data *data = dev->data;
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struct mec_uart_regs *const regs = devcfg->regs;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ERDAI, MEC_UART_IEN_FLAG_ERDAI);
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k_spin_unlock(&data->lock, key);
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}
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static inline void irq_rx_disable(const struct device *dev)
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{
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const struct uart_mec5_devcfg *const devcfg = dev->config;
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struct uart_mec5_dev_data *data = dev->data;
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struct mec_uart_regs *const regs = devcfg->regs;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ERDAI, 0);
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k_spin_unlock(&data->lock, key);
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}
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static int uart_mec5_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
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{
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const struct uart_mec5_devcfg *const devcfg = dev->config;
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struct uart_mec5_dev_data *data = dev->data;
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struct mec_uart_regs *const regs = devcfg->regs;
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int num_tx = 0, ret = 0;
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if (len < 0) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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while (num_tx < len) {
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ret = mec_hal_uart_tx_byte(regs, tx_data[num_tx]);
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if (ret == MEC_RET_ERR_BUSY) {
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break;
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}
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num_tx++;
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}
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if (data->tx_enabled) {
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irq_tx_enable(dev);
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}
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k_spin_unlock(&data->lock, key);
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return num_tx;
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}
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static int uart_mec5_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
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{
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const struct uart_mec5_devcfg *const devcfg = dev->config;
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struct uart_mec5_dev_data *data = dev->data;
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struct mec_uart_regs *const regs = devcfg->regs;
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int num_rx = 0, ret = 0;
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if (size < 0) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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uint8_t *pdata = rx_data;
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while (num_rx < size) {
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ret = mec_hal_uart_rx_byte(regs, pdata);
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if (ret != MEC_RET_OK) {
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break;
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}
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pdata++;
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num_rx++;
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}
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if (data->rx_enabled) {
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irq_rx_enable(dev);
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}
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k_spin_unlock(&data->lock, key);
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return num_rx;
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}
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static void uart_mec5_irq_tx_enable(const struct device *dev)
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{
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struct uart_mec5_dev_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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data->tx_enabled = 1;
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irq_tx_enable(dev);
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k_spin_unlock(&data->lock, key);
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}
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static void uart_mec5_irq_tx_disable(const struct device *dev)
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{
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struct uart_mec5_dev_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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irq_tx_disable(dev);
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data->tx_enabled = 0;
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k_spin_unlock(&data->lock, key);
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}
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static int uart_mec5_irq_tx_ready(const struct device *dev)
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{
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struct uart_mec5_dev_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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int ret = 0;
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if (data->ipend == MEC_UART_IPEND_TX) {
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ret = 1;
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}
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k_spin_unlock(&data->lock, key);
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return ret;
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}
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static void uart_mec5_irq_rx_enable(const struct device *dev)
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{
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struct uart_mec5_dev_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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data->rx_enabled = 1;
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irq_rx_enable(dev);
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k_spin_unlock(&data->lock, key);
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}
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static void uart_mec5_irq_rx_disable(const struct device *dev)
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{
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struct uart_mec5_dev_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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irq_rx_disable(dev);
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data->rx_enabled = 0;
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k_spin_unlock(&data->lock, key);
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}
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/* check if UART TX shift register is empty. Empty TX shift register indicates
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* the UART does not need clocks and can be put into a low power state.
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* return 1 nothing remains to be transmitted, 0 otherwise.
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*/
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static int uart_mec5_irq_tx_complete(const struct device *dev)
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{
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const struct uart_mec5_devcfg *const devcfg = dev->config;
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struct mec_uart_regs *const regs = devcfg->regs;
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struct uart_mec5_dev_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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int ret = mec_hal_uart_is_tx_empty(regs);
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k_spin_unlock(&data->lock, key);
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return ret;
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}
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static int uart_mec5_irq_rx_ready(const struct device *dev)
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{
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struct uart_mec5_dev_data *data = dev->data;
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int ret = 0;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
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if (data->ipend == MEC_UART_IPEND_RX_DATA) {
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ret = 1;
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}
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k_spin_unlock(&data->lock, key);
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return ret;
|
|
}
|
|
|
|
static void irq_error_enable(const struct device *dev, uint8_t enable)
|
|
{
|
|
const struct uart_mec5_devcfg *const devcfg = dev->config;
|
|
struct mec_uart_regs *const regs = devcfg->regs;
|
|
uint8_t msk = 0;
|
|
|
|
if (enable) {
|
|
msk = MEC_UART_IEN_FLAG_ELSI;
|
|
}
|
|
|
|
mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ELSI, msk);
|
|
}
|
|
|
|
/*
|
|
* Enable received line status interrupt active when one or more of the following errors
|
|
* occur: overrun, parity, framing, or break.
|
|
*/
|
|
static void uart_mec5_irq_err_enable(const struct device *dev)
|
|
{
|
|
struct uart_mec5_dev_data *data = dev->data;
|
|
k_spinlock_key_t key = k_spin_lock(&data->lock);
|
|
|
|
irq_error_enable(dev, 1u);
|
|
|
|
k_spin_unlock(&data->lock, key);
|
|
}
|
|
|
|
static void uart_mec5_irq_err_disable(const struct device *dev)
|
|
{
|
|
struct uart_mec5_dev_data *data = dev->data;
|
|
k_spinlock_key_t key = k_spin_lock(&data->lock);
|
|
|
|
irq_error_enable(dev, 0);
|
|
|
|
k_spin_unlock(&data->lock, key);
|
|
}
|
|
|
|
static int uart_mec5_irq_is_pending(const struct device *dev)
|
|
{
|
|
struct uart_mec5_dev_data *data = dev->data;
|
|
k_spinlock_key_t key = k_spin_lock(&data->lock);
|
|
int ret = 0;
|
|
|
|
if (data->ipend != MEC_UART_IPEND_NONE) {
|
|
ret = 1;
|
|
}
|
|
|
|
k_spin_unlock(&data->lock, key);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int uart_mec5_irq_update(const struct device *dev)
|
|
{
|
|
const struct uart_mec5_devcfg *const devcfg = dev->config;
|
|
struct mec_uart_regs *const regs = devcfg->regs;
|
|
struct uart_mec5_dev_data *data = dev->data;
|
|
k_spinlock_key_t key = k_spin_lock(&data->lock);
|
|
|
|
data->ipend = MEC_UART_IPEND_NONE;
|
|
mec_hal_uart_pending_status(regs, &data->ipend);
|
|
|
|
switch (data->ipend) {
|
|
case MEC_UART_IPEND_NONE:
|
|
break;
|
|
case MEC_UART_IPEND_TX:
|
|
irq_tx_disable(dev);
|
|
break;
|
|
case MEC_UART_IPEND_RX_DATA:
|
|
irq_rx_disable(dev);
|
|
break;
|
|
case MEC_UART_IPEND_RX_ERR:
|
|
irq_error_enable(dev, 0);
|
|
break;
|
|
case MEC_UART_IPEND_MODEM:
|
|
__fallthrough; /* fall through */
|
|
default:
|
|
k_panic();
|
|
break;
|
|
}
|
|
|
|
k_spin_unlock(&data->lock, key);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void uart_mec5_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
|
|
void *cb_data)
|
|
{
|
|
struct uart_mec5_dev_data *data = dev->data;
|
|
k_spinlock_key_t key = k_spin_lock(&data->lock);
|
|
|
|
data->cb = cb;
|
|
data->cb_data = cb_data;
|
|
|
|
k_spin_unlock(&data->lock, key);
|
|
}
|
|
|
|
static void uart_mec5_isr(const struct device *dev)
|
|
{
|
|
struct uart_mec5_dev_data *data = dev->data;
|
|
|
|
if (data->cb) {
|
|
data->cb(dev, data->cb_data);
|
|
}
|
|
}
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
|
|
static const struct uart_driver_api uart_mec5_driver_api = {
|
|
.poll_in = uart_mec5_poll_in,
|
|
.poll_out = uart_mec5_poll_out,
|
|
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
|
|
.configure = uart_mec5_configure,
|
|
.config_get = uart_mec5_config_get,
|
|
#endif
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.fifo_fill = uart_mec5_fifo_fill,
|
|
.fifo_read = uart_mec5_fifo_read,
|
|
.irq_tx_enable = uart_mec5_irq_tx_enable,
|
|
.irq_tx_disable = uart_mec5_irq_tx_disable,
|
|
.irq_tx_ready = uart_mec5_irq_tx_ready,
|
|
.irq_rx_enable = uart_mec5_irq_rx_enable,
|
|
.irq_rx_disable = uart_mec5_irq_rx_disable,
|
|
.irq_tx_complete = uart_mec5_irq_tx_complete,
|
|
.irq_rx_ready = uart_mec5_irq_rx_ready,
|
|
.irq_err_enable = uart_mec5_irq_err_enable,
|
|
.irq_err_disable = uart_mec5_irq_err_disable,
|
|
.irq_is_pending = uart_mec5_irq_is_pending,
|
|
.irq_update = uart_mec5_irq_update,
|
|
.irq_callback_set = uart_mec5_irq_callback_set,
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
};
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#define UART_MEC5_CONFIGURE(n) \
|
|
do { \
|
|
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), uart_mec5_isr, \
|
|
DEVICE_DT_INST_GET(n), 0); \
|
|
\
|
|
irq_enable(DT_INST_IRQN(n)); \
|
|
} while (0)
|
|
#else
|
|
#define UART_MEC5_CONFIGURE(n)
|
|
#endif
|
|
|
|
#define UART_MEC5_DCFG_FLAGS(i) \
|
|
((DT_INST_ENUM_IDX_OR(i, rx_fifo_trig, 2) & 0x3u) | \
|
|
((DT_INST_PROP_OR(i, fifo_mode_disable, 0) & 0x1u) << 4) | \
|
|
((DT_INST_PROP_OR(i, use_extclk, 0) & 0x1u) << 5))
|
|
|
|
#define DEV_DATA_FLOW_CTRL(n) DT_INST_PROP_OR(n, hw_flow_control, UART_CFG_FLOW_CTRL_NONE)
|
|
|
|
#define UART_MEC5_DEVICE(i) \
|
|
PINCTRL_DT_INST_DEFINE(i); \
|
|
static const struct uart_mec5_devcfg uart_mec5_##i##_devcfg = { \
|
|
.regs = (struct mec_uart_regs *)DT_INST_REG_ADDR(i), \
|
|
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(i), \
|
|
.clock_freq = DT_INST_PROP_OR(i, clock_frequency, UART_MEC_DFLT_CLK_FREQ), \
|
|
.flags = UART_MEC5_DCFG_FLAGS(i), \
|
|
}; \
|
|
static struct uart_mec5_dev_data uart_mec5_##i##_dev_data = { \
|
|
.ucfg.baudrate = DT_INST_PROP_OR(i, current_speed, 0), \
|
|
.ucfg.parity = UART_CFG_PARITY_NONE, \
|
|
.ucfg.stop_bits = UART_CFG_STOP_BITS_1, \
|
|
.ucfg.data_bits = UART_CFG_DATA_BITS_8, \
|
|
.ucfg.flow_ctrl = DEV_DATA_FLOW_CTRL(i), \
|
|
}; \
|
|
static int uart_mec5_##i##_init(const struct device *dev) \
|
|
{ \
|
|
UART_MEC5_CONFIGURE(i); \
|
|
return uart_mec5_init(dev); \
|
|
} \
|
|
DEVICE_DT_INST_DEFINE(i, uart_mec5_##i##_init, NULL, &uart_mec5_##i##_dev_data, \
|
|
&uart_mec5_##i##_devcfg, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
|
|
&uart_mec5_driver_api);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(UART_MEC5_DEVICE)
|