680fa154bf
This driver could end up doing a great deal of work inside the ISR when large SPI transfers were in use, which could cause significant IRQ latency. For the normal, non-async SPI transfer case, use events to signal the calling thread to complete the work rather than performing FIFO transfers inside the ISR. Signed-off-by: Robert Hancock <robert.hancock@calian.com>
12 lines
305 B
Text
12 lines
305 B
Text
# Xilinx SPI
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# Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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config SPI_XLNX_AXI_QUADSPI
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bool "Xilinx AXI Quad SPI driver"
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default y
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depends on DT_HAS_XLNX_XPS_SPI_2_00_A_ENABLED
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select EVENTS
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help
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Enable Xilinx AXI Quad SPI v3.2 driver.
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