6d06a8cea9
Although we can get the number of configured OUT and IN endpoints and endpoint capabilities from the DWC GHWCFGn registers, we need to configure the number of endpoint configuration structs at build time. On some platforms, we cannot access the hardware register at pre-init, so we use the GHWCFGn values from the devicetree to provide endpoint capabilities. This can be considered a workaround, and we may change the upper layer internals to avoid it in the future. Also, add a new vendor quirk to fill in platform-specific controller capabilities. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
275 lines
6.4 KiB
Text
275 lines
6.4 KiB
Text
/*
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* SPDX-License-Identifier: Apache-2.0
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* Copyright (C) 2022, Intel Corporation
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* Description:
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* Section of the DTS file containing definitions for the HPS
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* heavily modified for Zephyr
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*/
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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eth0 = &gmac0;
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usb = &usb1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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/* next-level-cache = <&L2>; */ /*cache driver not available yet */
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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/* next-level-cache = <&L2>; */ /*cache driver not available yet */
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};
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};
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intc: intc@fffed000 {
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compatible = "arm,gic-v1", "arm,gic";
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#interrupt-cells = <4>;
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interrupt-controller;
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reg = <0xfffed000 0x1000>,
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<0xfffec100 0x100>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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device_type = "soc";
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interrupt-parent = <&intc>;
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ranges;
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L2: l2-cache@fffef000 {
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compatible = "arm,pl330-cache";
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reg = <0xfffef000 0x1000>;
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interrupts = <0 38 0x04 IRQ_DEFAULT_PRIORITY>;
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status= "okay";
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};
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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clocks {
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osc1: osc1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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osc2: osc2 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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f2s_periph_ref_clk: f2s_periph_ref_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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f2s_sdram_ref_clk: f2s_sdram_ref_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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};
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};
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sysmgr: sysmgr@ffd08000 {
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compatible = "altr,sys-mgr", "syscon";
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reg = <0xffd08000 0x4000>;
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status = "okay";
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};
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ocram: sram@ffff0000 {
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compatible = "zephyr,memory-region" , "mmio-sram";
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reg = <0xffff0000 0x10000>;
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zephyr,memory-region = "OCRAM";
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};
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arch_timer: timer@fffec200 {
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compatible = "arm,armv8-timer";
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status = "okay";
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interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3";
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interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>;
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reg = <0xfffec200 0x1C>;
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clocks = <&osc1>;
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};
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uart0: serial0@ffc02000 {
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compatible = "ns16550","snps,dw-apb-uart";
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reg = <0xffc02000 0x1000>;
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interrupts = <0 162 4 IRQ_DEFAULT_PRIORITY>;
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reg-shift = <2>;
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clock-frequency = <100000000>;
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dma-names = "tx", "rx";
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};
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uart1: serial1@ffc03000 {
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compatible = "ns16550","snps,dw-apb-uart";
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reg = <0xffc03000 0x1000>;
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interrupts = <0 163 4 IRQ_DEFAULT_PRIORITY>;
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reg-shift = <2>;
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clock-frequency = <100000000>;
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dma-names = "tx", "rx";
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};
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gmac0: ethernet@ff700000 {
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compatible = "snps,ethernet-cyclonev";
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reg = <0xff700000 0x2000>;
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interrupts = <0 115 4 IRQ_DEFAULT_PRIORITY>;
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emac-index = <0>;
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status = "disabled";
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};
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gmac1: ethernet@ff702000 {
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compatible = "snps,ethernet-cyclonev";
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reg = <0xff702000 0x2000>;
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interrupts = <0 120 4 IRQ_DEFAULT_PRIORITY>;
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emac-index = <1>;
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status = "disabled";
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};
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gpio0: gpio@ff708000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-gpio";
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reg = <0xff708000 0x1000>;
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interrupts = <0 164 4 IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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ngpios = <29>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@ff709000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-gpio";
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reg = <0xff709000 0x1000>;
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interrupts = <0 165 4 IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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ngpios = <29>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: gpio@ff70a000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-gpio";
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reg = <0xff70a000 0x1000>;
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interrupts = <0 166 4 IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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ngpios = <27>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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i2c0: i2c@ffc04000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc04000 0x1000>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <0 158 0x4 IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&intc>;
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status = "okay";
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};
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i2c1: i2c@ffc05000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc05000 0x1000>;
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interrupts = <0 159 0x4 IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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i2c2: i2c@ffc06000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc06000 0x1000>;
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interrupts = <0 160 0x4 IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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i2c3: i2c@ffc07000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc07000 0x1000>;
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interrupts = <0 161 0x4 IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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usb0: usb@ffb30000 {
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compatible = "snps,dwc2";
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reg = <0xffb30000 0xffff>;
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interrupts = <0 127 4 IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&intc>;
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num-out-eps = <16>;
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num-in-eps = <16>;
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ghwcfg1 = <0x00000000>;
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ghwcfg2 = <0x208ffc90>;
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ghwcfg4 = <0xfe0f0020>;
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status = "disabled";
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};
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usb1: usb@ffb40000 {
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compatible = "snps,dwc2";
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reg = <0xffb40000 0xffff>;
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interrupts = <0 128 4 IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&intc>;
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num-out-eps = <16>;
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num-in-eps = <16>;
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ghwcfg1 = <0x00000000>;
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ghwcfg2 = <0x208ffc90>;
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ghwcfg4 = <0xfe0f0020>;
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status = "okay";
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};
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spi0: spi@fff00000 {
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compatible = "snps,designware-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfff00000 0x1000>;
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fifo-depth = <256>;
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max-xfer-size = <32>;
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interrupts = <0 154 4 IRQ_DEFAULT_PRIORITY>;
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clock-frequency = <200000000>;
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status = "okay";
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};
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spi1: spi@fff01000 {
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compatible = "snps,designware-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfff01000 0x1000>;
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fifo-depth = <256>;
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max-xfer-size = <32>;
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interrupts = <0 155 4 IRQ_DEFAULT_PRIORITY>;
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clock-frequency = <200000000>;
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status = "disabled";
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};
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};
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};
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