a819bfb2d5
Rename the remaining z_xtensa stuff as these are (mostly) under arch/xtensa. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
516 lines
14 KiB
Python
516 lines
14 KiB
Python
#!/usr/bin/env python3
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#
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# Copyright (c) 2021 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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import binascii
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import logging
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import struct
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import sys
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from enum import Enum
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from gdbstubs.gdbstub import GdbStub
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logger = logging.getLogger("gdbstub")
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# Matches same in coredump.c
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XTENSA_BLOCK_HDR_DUMMY_SOC = 255
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# Must match --soc arg options; see get_soc
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class XtensaSoc(Enum):
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UNKNOWN = 0
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SAMPLE_CONTROLLER = 1
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ESP32 = 2
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INTEL_ADSP_CAVS = 3
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ESP32S2 = 4
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ESP32S3 = 5
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DC233C = 6
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# The previous version of this script didn't need to know
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# what toolchain Zephyr was built with; it assumed sample_controller
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# was built with the Zephyr SDK and ESP32 with Espressif's.
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# However, if a SOC can be built by two separate toolchains,
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# there is a chance that the GDBs provided by the toolchains will
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# assign different indices to the same registers. For example, the
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# Intel ADSP family of SOCs can be built with both Zephyr's
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# SDK and Cadence's XCC toolchain. With the same SOC APL,
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# the SDK's GDB assigns PC the index 0, while XCC's GDB assigns
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# it the index 32.
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#
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# (The Espressif value isn't really required, since ESP32 can
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# only be built with Espressif's toolchain, but it's included for
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# completeness.)
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class XtensaToolchain(Enum):
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UNKNOWN = 0
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ZEPHYR = 1
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XCC = 2
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ESPRESSIF = 3
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def get_gdb_reg_definition(soc, toolchain):
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if soc == XtensaSoc.SAMPLE_CONTROLLER:
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return GdbRegDef_Sample_Controller
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elif soc == XtensaSoc.ESP32:
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return GdbRegDef_ESP32
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elif soc == XtensaSoc.INTEL_ADSP_CAVS:
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if toolchain == XtensaToolchain.ZEPHYR:
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return GdbRegDef_Intel_Adsp_CAVS_Zephyr
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elif toolchain == XtensaToolchain.XCC:
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return GdbRegDef_Intel_Adsp_CAVS_XCC
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elif toolchain == XtensaToolchain.ESPRESSIF:
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logger.error("Can't use espressif toolchain with CAVS. " +
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"Use zephyr or xcc instead. Exiting...")
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sys.exit(1)
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else:
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raise NotImplementedError
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elif soc == XtensaSoc.ESP32S2:
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return GdbRegDef_ESP32S2
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elif soc == XtensaSoc.ESP32S3:
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return GdbRegDef_ESP32S3
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elif soc == XtensaSoc.DC233C:
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return GdbRegDef_DC233C
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else:
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raise NotImplementedError
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class ExceptionCodes(Enum):
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# Matches arch/xtensa/core/fatal.c->xtensa_exccause
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ILLEGAL_INSTRUCTION = 0
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# Syscall not fatal
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INSTR_FETCH_ERROR = 2
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LOAD_STORE_ERROR = 3
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# Level-1 interrupt not fatal
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ALLOCA = 5
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DIVIDE_BY_ZERO = 6
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PRIVILEGED = 8
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LOAD_STORE_ALIGNMENT = 9
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INSTR_PIF_DATA_ERROR = 12
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LOAD_STORE_PIF_DATA_ERROR = 13
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INSTR_PIF_ADDR_ERROR = 14
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LOAD_STORE_PIF_ADDR_ERROR = 15
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INSTR_TLB_MISS = 16
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INSTR_TLB_MULTI_HIT = 17
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INSTR_FETCH_PRIVILEGE = 18
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INST_FETCH_PROHIBITED = 20
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LOAD_STORE_TLB_MISS = 24
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LOAD_STORE_TLB_MULTI_HIT = 25
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LOAD_STORE_PRIVILEGE = 26
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LOAD_PROHIBITED = 28
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STORE_PROHIBITED = 29
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# Coprocessor disabled spans 32 - 39
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COPROCESSOR_DISABLED_START = 32
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COPROCESSOR_DISABLED_END = 39
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Z_EXCEPT_REASON = 63
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# Others (reserved / unknown) map to default signal
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class GdbStub_Xtensa(GdbStub):
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GDB_SIGNAL_DEFAULT = 7
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# Mapping based on section 4.4.1.5 of the
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# Xtensa ISA Reference Manual (Table 4–64. Exception Causes)
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# Somewhat arbitrary; included only because GDB requests it
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GDB_SIGNAL_MAPPING = {
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ExceptionCodes.ILLEGAL_INSTRUCTION: 4,
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ExceptionCodes.INSTR_FETCH_ERROR: 7,
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ExceptionCodes.LOAD_STORE_ERROR: 11,
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ExceptionCodes.ALLOCA: 7,
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ExceptionCodes.DIVIDE_BY_ZERO: 8,
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ExceptionCodes.PRIVILEGED: 11,
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ExceptionCodes.LOAD_STORE_ALIGNMENT: 7,
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ExceptionCodes.INSTR_PIF_DATA_ERROR: 7,
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ExceptionCodes.LOAD_STORE_PIF_DATA_ERROR: 7,
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ExceptionCodes.INSTR_PIF_ADDR_ERROR: 11,
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ExceptionCodes.LOAD_STORE_PIF_ADDR_ERROR: 11,
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ExceptionCodes.INSTR_TLB_MISS: 11,
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ExceptionCodes.INSTR_TLB_MULTI_HIT: 11,
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ExceptionCodes.INSTR_FETCH_PRIVILEGE: 11,
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ExceptionCodes.INST_FETCH_PROHIBITED: 11,
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ExceptionCodes.LOAD_STORE_TLB_MISS: 11,
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ExceptionCodes.LOAD_STORE_TLB_MULTI_HIT: 11,
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ExceptionCodes.LOAD_STORE_PRIVILEGE: 11,
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ExceptionCodes.LOAD_PROHIBITED: 11,
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ExceptionCodes.STORE_PROHIBITED: 11,
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ExceptionCodes.Z_EXCEPT_REASON: 6,
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}
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reg_fmt = "<I"
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def __init__(self, logfile, elffile):
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super().__init__(logfile=logfile, elffile=elffile)
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self.registers = None
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self.exception_code = None
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self.gdb_signal = self.GDB_SIGNAL_DEFAULT
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self.parse_arch_data_block()
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self.compute_signal()
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def parse_arch_data_block(self):
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arch_data_blk = self.logfile.get_arch_data()['data']
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self.version = struct.unpack('H', arch_data_blk[1:3])[0]
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logger.debug("Xtensa GDB stub version: %d" % self.version)
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# Get SOC and toolchain to get correct format for unpack
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self.soc = XtensaSoc(bytearray(arch_data_blk)[0])
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logger.debug("Xtensa SOC: %s" % self.soc.name)
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if self.version >= 2:
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self.toolchain = XtensaToolchain(bytearray(arch_data_blk)[3])
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arch_data_blk_regs = arch_data_blk[4:]
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else:
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# v1 only supported ESP32 and sample_controller, each of which
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# only build with one toolchain
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if self.soc == XtensaSoc.ESP32:
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self.toolchain = XtensaToolchain.ESPRESSIF
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else:
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self.toolchain = XtensaToolchain.ZEPHYR
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arch_data_blk_regs = arch_data_blk[3:]
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logger.debug("Xtensa toolchain: %s" % self.toolchain.name)
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self.gdb_reg_def = get_gdb_reg_definition(self.soc, self.toolchain)
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tu = struct.unpack(self.gdb_reg_def.ARCH_DATA_BLK_STRUCT_REGS,
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arch_data_blk_regs)
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self.registers = dict()
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self.map_registers(tu)
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def map_registers(self, tu):
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i = 0
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for r in self.gdb_reg_def.RegNum:
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reg_num = r.value
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# Dummy WINDOWBASE and WINDOWSTART to enable GDB
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# without dumping them and all AR registers;
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# avoids interfering with interrupts / exceptions
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if r == self.gdb_reg_def.RegNum.WINDOWBASE:
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self.registers[reg_num] = 0
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elif r == self.gdb_reg_def.RegNum.WINDOWSTART:
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self.registers[reg_num] = 1
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else:
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if r == self.gdb_reg_def.RegNum.EXCCAUSE:
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self.exception_code = tu[i]
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self.registers[reg_num] = tu[i]
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i += 1
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def compute_signal(self):
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sig = self.GDB_SIGNAL_DEFAULT
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code = ExceptionCodes(self.exception_code)
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if code is None:
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sig = self.GDB_SIGNAL_DEFAULT
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if code in self.GDB_SIGNAL_MAPPING:
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sig = self.GDB_SIGNAL_MAPPING[code]
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elif ExceptionCodes.COPROCESSOR_DISABLED_START.value <= code <= \
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ExceptionCodes.COPROCESSOR_DISABLED_END.value:
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sig = 8
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self.gdb_signal = sig
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def handle_register_group_read_packet(self):
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idx = 0
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pkt = b''
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GDB_G_PKT_MAX_REG = \
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max([reg_num.value for reg_num in self.gdb_reg_def.RegNum])
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# We try to send as many of the registers listed
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# as possible, but we are constrained by the
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# maximum length of the g packet
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while idx <= GDB_G_PKT_MAX_REG and idx * 4 < self.gdb_reg_def.SOC_GDB_GPKT_BIN_SIZE:
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if idx in self.registers:
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bval = struct.pack(self.reg_fmt, self.registers[idx])
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pkt += binascii.hexlify(bval)
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else:
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pkt += b'x' * 8
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idx += 1
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self.put_gdb_packet(pkt)
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def handle_register_single_read_packet(self, pkt):
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# format is pXX, where XX is the hex representation of the idx
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regIdx = int('0x' + pkt[1:].decode('utf8'), 16)
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try:
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bval = struct.pack(self.reg_fmt, self.registers[regIdx])
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self.put_gdb_packet(binascii.hexlify(bval))
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except KeyError:
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self.put_gdb_packet(b'x' * 8)
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# The following classes map registers to their index used by
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# the GDB of a specific SOC and toolchain. See xtensa_config.c.
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# WARNING: IF YOU CHANGE THE ORDER OF THE REGISTERS IN ONE
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# MAPPING, YOU MUST CHANGE THE ORDER TO MATCH IN THE OTHERS
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# AND IN arch/xtensa/core/coredump.c's xtensa_arch_block.r.
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# See map_registers.
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# For the same reason, even though the WINDOWBASE and WINDOWSTART
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# values are dummied by this script, they have to be last in the
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# mapping below.
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# sample_controller is unique to Zephyr SDK
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# sdk-ng -> overlays/xtensa_sample_controller/gdb/gdb/xtensa-config.c
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class GdbRegDef_Sample_Controller:
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ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIIII'
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# This fits the maximum possible register index (110).
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# Unlike on ESP32 GDB, there doesn't seem to be an
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# actual hard limit to how big the g packet can be.
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SOC_GDB_GPKT_BIN_SIZE = 444
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class RegNum(Enum):
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PC = 0
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EXCCAUSE = 77
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EXCVADDR = 83
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SAR = 33
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PS = 38
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SCOMPARE1 = 39
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A0 = 89
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A1 = 90
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A2 = 91
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A3 = 92
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A4 = 93
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A5 = 94
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A6 = 95
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A7 = 96
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A8 = 97
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A9 = 98
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A10 = 99
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A11 = 100
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A12 = 101
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A13 = 102
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A14 = 103
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A15 = 104
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# LBEG, LEND, and LCOUNT not on sample_controller
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WINDOWBASE = 34
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WINDOWSTART = 35
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# ESP32 is unique to espressif toolchain
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# espressif xtensa-overlays -> xtensa_esp32/gdb/gdb/xtensa-config.c
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class GdbRegDef_ESP32:
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ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIIIIIII'
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SOC_GDB_GPKT_BIN_SIZE = 420
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class RegNum(Enum):
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PC = 0
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EXCCAUSE = 143
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EXCVADDR = 149
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SAR = 68
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PS = 73
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SCOMPARE1 = 76
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A0 = 157
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A1 = 158
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A2 = 159
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A3 = 160
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A4 = 161
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A5 = 162
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A6 = 163
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A7 = 164
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A8 = 165
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A9 = 166
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A10 = 167
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A11 = 168
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A12 = 169
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A13 = 170
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A14 = 171
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A15 = 172
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LBEG = 65
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LEND = 66
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LCOUNT = 67
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WINDOWBASE = 69
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WINDOWSTART = 70
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class GdbRegDef_ESP32S2:
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ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIII'
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SOC_GDB_GPKT_BIN_SIZE = 420
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class RegNum(Enum):
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PC = 0
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EXCCAUSE = 99
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EXCVADDR = 115
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SAR = 65
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PS = 70
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A0 = 155
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A1 = 156
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A2 = 157
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A3 = 158
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A4 = 159
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A5 = 160
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A6 = 161
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A7 = 162
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A8 = 163
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A9 = 164
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A10 = 165
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A11 = 166
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A12 = 167
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A13 = 168
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A14 = 169
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A15 = 170
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WINDOWBASE = 66
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WINDOWSTART = 67
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class GdbRegDef_ESP32S3:
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ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIIIIIII'
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SOC_GDB_GPKT_BIN_SIZE = 420
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class RegNum(Enum):
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PC = 0
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EXCCAUSE = 166
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EXCVADDR = 172
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SAR = 68
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PS = 73
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SCOMPARE1 = 76
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A0 = 212
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A1 = 213
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A2 = 214
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A3 = 215
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A4 = 216
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A5 = 217
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A6 = 218
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A7 = 219
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A8 = 220
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A9 = 221
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A10 = 222
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A11 = 223
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A12 = 224
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A13 = 225
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A14 = 226
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A15 = 227
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LBEG = 65
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LEND = 66
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LCOUNT = 67
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WINDOWBASE = 69
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WINDOWSTART = 70
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# sdk-ng -> overlays/xtensa_intel_apl/gdb/gdb/xtensa-config.c
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class GdbRegDef_Intel_Adsp_CAVS_Zephyr:
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ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIIIIIII'
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# If you send all the registers below (up to index 173)
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# GDB incorrectly assigns 0 to EXCCAUSE / EXCVADDR... for some
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# reason. Since APL GDB sends p packets for every An register
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# even if it was sent in the g packet, I arbitrarily shrunk the
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# G packet to include up to A1, which fixed the issue.
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SOC_GDB_GPKT_BIN_SIZE = 640
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class RegNum(Enum):
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PC = 0
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EXCCAUSE = 148
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EXCVADDR = 154
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SAR = 68
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PS = 74
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SCOMPARE1 = 77
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A0 = 158
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A1 = 159
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A2 = 160
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A3 = 161
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A4 = 162
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A5 = 163
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A6 = 164
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A7 = 165
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A8 = 166
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A9 = 167
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A10 = 168
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A11 = 169
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A12 = 170
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A13 = 171
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A14 = 172
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A15 = 173
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LBEG = 65
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LEND = 66
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LCOUNT = 67
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WINDOWBASE = 70
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WINDOWSTART = 71
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# Reverse-engineered from:
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# sof -> src/debug/gdb/gdb.c
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# sof -> src/arch/xtensa/include/xtensa/specreg.h
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class GdbRegDef_Intel_Adsp_CAVS_XCC:
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ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIIIIIII'
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# xt-gdb doesn't use the g packet at all
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SOC_GDB_GPKT_BIN_SIZE = 0
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class RegNum(Enum):
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PC = 32
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EXCCAUSE = 744
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EXCVADDR = 750
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SAR = 515
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PS = 742
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SCOMPARE1 = 524
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A0 = 256
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A1 = 257
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A2 = 258
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A3 = 259
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A4 = 260
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A5 = 261
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A6 = 262
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A7 = 263
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A8 = 264
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A9 = 265
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A10 = 266
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A11 = 267
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A12 = 268
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A13 = 269
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A14 = 270
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A15 = 271
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LBEG = 512
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LEND = 513
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LCOUNT = 514
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WINDOWBASE = 584
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WINDOWSTART = 585
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# sdk-ng -> overlays/xtensa_dc233c/gdb/gdb/xtensa-config.c
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class GdbRegDef_DC233C:
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ARCH_DATA_BLK_STRUCT_REGS = '<IIIIIIIIIIIIIIIIIIIIIIIII'
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SOC_GDB_GPKT_BIN_SIZE = 568
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class RegNum(Enum):
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PC = 0
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EXCCAUSE = 93
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EXCVADDR = 99
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SAR = 36
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PS = 42
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SCOMPARE1 = 44
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A0 = 105
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A1 = 106
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A2 = 107
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A3 = 108
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A4 = 109
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A5 = 110
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A6 = 111
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A7 = 112
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A8 = 113
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A9 = 114
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A10 = 115
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A11 = 116
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A12 = 117
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A13 = 118
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A14 = 119
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A15 = 120
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LBEG = 33
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LEND = 34
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LCOUNT = 35
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WINDOWBASE = 38
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WINDOWSTART = 39
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