zephyr/dts/riscv
Jilay Pandya f2f195de55 dts: bindings: i2s: replace underscore with hyphen
replace underscore with hyphen as per device tree specification

Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
2025-01-15 19:06:06 +01:00
..
andes dts/andes: adjust the sizes of PLIC nodes 2024-10-31 14:17:02 -05:00
efinix dts: riscv: Fix incorrect plic size 2024-07-02 22:21:17 -04:00
espressif soc: esp32c6: Add GP timers support 2024-12-21 05:52:20 +01:00
gd dts/riscv: add riscv compatible string where it's missing 2024-01-31 10:41:49 +01:00
ite dts: ite: refactor the it8801 template hierarchy 2024-12-31 19:45:49 +01:00
lowrisc dts: opentitan: update plic interrupt count to match spec 2024-03-22 09:23:46 +00:00
microchip dts: mbox: add PolarFire SoC mailbox interface 2024-02-01 04:33:16 -05:00
niosv dts/riscv: add riscv compatible string where it's missing 2024-01-31 10:41:49 +01:00
nordic dts: risc-v: nordic: nrf54h20_cpuppr: fix cpuflpr_vevif label assignment 2025-01-07 11:53:01 +01:00
openisa soc/openisa: enable the C extension 2024-07-03 15:06:14 -04:00
qemu arch: riscv64: smp: get msip base address from dts 2024-11-27 06:58:57 -05:00
sensry dts: sensry: add pinctrl 2025-01-09 04:04:06 +01:00
sifive boards: hifive_unmatched: add support for S7 and U74 targets 2024-11-20 10:15:03 +00:00
starfive dts: jh7110: fix memory definitions 2024-04-09 14:20:39 +02:00
telink drivers: intc: plic: define all registers' offset in the driver 2023-10-04 09:06:28 -04:00
wch dts: riscv: include riscv,cpus.yaml in qingke-v2 2025-01-15 11:58:58 +01:00
neorv32.dtsi dts/riscv: add riscv compatible string where it's missing 2024-01-31 10:41:49 +01:00
renode_riscv32_virt.dtsi dts: riscv: add a SoC dtsi for Renode RISC-V Virt SoC 2024-01-08 12:35:10 +01:00
riscv32-litex-vexriscv.dtsi dts: bindings: i2s: replace underscore with hyphen 2025-01-15 19:06:06 +01:00