f51729aada
Add a GPIO driver for the Microchip MEC5 HAL based chips. Current devices are: MEC174x, MEC175x, and HAL version of MEC172x named MECH172x. Signed-off-by: Scott Worley <scott.worley@microchip.com>
529 lines
16 KiB
C
529 lines
16 KiB
C
/*
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* Copyright (c) 2024 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_mec5_gpio
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#include <errno.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
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#include <soc.h>
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#include <zephyr/irq.h>
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#include <mec_gpio_api.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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/* 32 pins per bank. Each pin has a 4-byte control register */
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#define MEC5_GPIO_PIN_CTRL_RSHFT 7
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#define MEC5_GPIO_PIN_CTRL_ADDR_MSK 0xfu
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struct gpio_mec5_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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};
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struct gpio_mec5_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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uintptr_t pcr1_base;
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uintptr_t parin_addr;
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uintptr_t parout_addr;
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uint32_t flags;
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};
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static inline uint32_t mec5_addr_to_port(uint32_t base_addr)
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{
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return ((base_addr >> MEC5_GPIO_PIN_CTRL_RSHFT) & MEC5_GPIO_PIN_CTRL_ADDR_MSK);
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}
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/* NOTE: gpio_flags_t b[0:15] are defined in the dt-binding gpio header.
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* b[31:16] are defined in the driver gpio header.
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*/
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static int gpio_mec5_validate_flags(gpio_flags_t flags)
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{
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if (flags & GPIO_LINE_OPEN_SOURCE) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_OUTPUT_INIT_LOW) && (flags & GPIO_OUTPUT_INIT_HIGH)) {
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return -EINVAL;
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}
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return 0;
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}
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static const struct mec_gpio_props cfg_props_init[] = {
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{MEC_GPIO_PWRGT_PROP_ID, MEC_GPIO_PROP_PWRGT_VTR},
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{MEC_GPIO_OSEL_PROP_ID, MEC_GPIO_PROP_OSEL_CTRL},
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{MEC_GPIO_INPAD_DIS_PROP_ID, MEC_GPIO_PROP_INPAD_EN},
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};
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/* Each GPIO pin has two 32-bit control registers. Control 1 configures pin
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* features except for drive strength and slew rate in Control 2.
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* A pin's input and output state can be read/written from either the Control 1
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* register or from corresponding bits in the GPIO parallel input/output registers.
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* The parallel input and output registers group 32 pins into each register.
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* The GPIO hardware restricts the pin output state to Control 1 or the parallel bit.
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* Both output bits reflect each other on read and writes but only one is writable
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* selected by the output control select bit in Control 1. In the configuration API
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* we use Control 1 to configure all pin features and output state. Before exiting,
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* we set the output select for parallel mode enabling writes to the parallel output bit.
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*/
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static int gpio_mec5_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_mec5_config *config = dev->config;
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uint32_t pin_num = 0u;
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uint32_t port_num = 0u;
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uint32_t temp = 0u;
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int ret = 0;
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size_t idx = 0;
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struct mec_gpio_props props[8];
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port_num = mec5_addr_to_port(config->pcr1_base);
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ret = mec_hal_gpio_pin_num(port_num, pin, &pin_num);
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if (ret != MEC_RET_OK) {
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return -EINVAL;
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}
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ret = mec_hal_gpio_port_pin_valid(port_num, pin);
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if (ret != MEC_RET_OK) {
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return -EINVAL;
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}
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ret = gpio_mec5_validate_flags(flags);
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if (ret) {
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return ret;
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}
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if (flags == GPIO_DISCONNECTED) {
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ret = mec_hal_gpio_set_property(pin_num, MEC_GPIO_PWRGT_PROP_ID,
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MEC_GPIO_PROP_PWRGT_OFF);
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if (ret != MEC_RET_OK) {
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ret = -EIO;
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}
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return ret;
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}
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ret = mec_hal_gpio_set_props(pin_num, cfg_props_init, ARRAY_SIZE(cfg_props_init));
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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if (flags & GPIO_OUTPUT) {
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props[idx].prop = MEC_GPIO_DIR_PROP_ID;
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props[idx].val = MEC_GPIO_PROP_DIR_OUT;
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idx++;
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props[idx].prop = MEC_GPIO_OBUFT_PROP_ID;
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props[idx].val = MEC_GPIO_PROP_PUSH_PULL;
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if (flags & GPIO_LINE_OPEN_DRAIN) {
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props[idx].val = MEC_GPIO_PROP_OPEN_DRAIN;
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}
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idx++;
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props[idx].prop = MEC_GPIO_CTRL_OUT_VAL_ID;
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props[idx].val = 0u;
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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props[idx].val = 1u;
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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props[idx].val = 0u;
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} else {
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mec_hal_gpio_pad_in(pin_num, &props[idx].val);
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}
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idx++;
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}
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if (flags & GPIO_INPUT) {
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props[idx].prop = MEC_GPIO_DIR_PROP_ID;
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props[idx].val = MEC_GPIO_PROP_DIR_IN;
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idx++;
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}
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temp = flags & (GPIO_PULL_UP | GPIO_PULL_DOWN);
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if (temp) {
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props[idx].prop = MEC_GPIO_PUD_PROP_ID;
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if (temp == (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
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props[idx].val = MEC_GPIO_PROP_REPEATER;
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} else if (temp & GPIO_PULL_UP) {
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props[idx].val = MEC_GPIO_PROP_PULL_UP;
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} else {
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props[idx].val = MEC_GPIO_PROP_PULL_DN;
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}
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idx++;
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}
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ret = mec_hal_gpio_set_props(pin_num, props, idx);
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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/* make output state in control read-only in control and read-write in parallel reg */
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ret = mec_hal_gpio_set_property(pin_num, MEC_GPIO_OSEL_PROP_ID, MEC_GPIO_PROP_OSEL_PAROUT);
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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return 0;
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}
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static uint8_t gen_gpio_ctrl_icfg(enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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uint8_t idet;
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if (mode == GPIO_INT_MODE_DISABLED) {
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idet = MEC_GPIO_PROP_IDET_DIS;
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} else {
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if (mode == GPIO_INT_MODE_LEVEL) {
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if (trig == GPIO_INT_TRIG_HIGH) {
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idet = MEC_GPIO_PROP_IDET_HI_LVL;
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} else {
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idet = MEC_GPIO_PROP_IDET_LO_LVL;
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}
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} else {
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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idet = MEC_GPIO_PROP_IDET_EDGE_DN;
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break;
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case GPIO_INT_TRIG_HIGH:
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idet = MEC_GPIO_PROP_IDET_EDGE_UP;
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break;
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case GPIO_INT_TRIG_BOTH:
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idet = MEC_GPIO_PROP_IDET_EDGE_BOTH;
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break;
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default:
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idet = MEC_GPIO_PROP_IDET_DIS;
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break;
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}
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}
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}
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return idet;
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}
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/* Enable interrupt to propagate via its GIRQ to the NVIC */
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static void gpio_mec5_intr_en(uint8_t port, gpio_pin_t pin, enum gpio_int_mode mode)
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{
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uint8_t en = 0u;
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if (mode != GPIO_INT_MODE_DISABLED) {
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en = 1u;
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}
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mec_hal_gpio_port_pin_ia_enable(port, pin, en);
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}
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static const struct mec_gpio_props icfg_props_init[] = {
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{MEC_GPIO_PWRGT_PROP_ID, MEC_GPIO_PROP_PWRGT_VTR},
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{MEC_GPIO_INPAD_DIS_PROP_ID, MEC_GPIO_PROP_INPAD_EN},
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};
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static int gpio_mec5_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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const struct gpio_mec5_config *config = dev->config;
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uint32_t pin_num = (uint32_t)MEC_PIN_MAX;
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uint32_t port_num = 0;
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int ret = 0;
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uint8_t idet = 0, idet_curr = 0;
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/* Validate pin number range in terms of current port */
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port_num = mec5_addr_to_port(config->pcr1_base);
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ret = mec_hal_gpio_port_pin_valid(port_num, pin);
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if (ret != MEC_RET_OK) {
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return -EINVAL;
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}
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/* Check if GPIO port supports interrupts */
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if ((mode != GPIO_INT_MODE_DISABLED) && !(config->flags & GPIO_INT_ENABLE)) {
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return -ENOTSUP;
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}
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/* Disable interrupt in the EC aggregator */
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gpio_mec5_intr_en(port_num, pin, 0);
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mec_hal_gpio_pin_num(port_num, pin, &pin_num);
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ret = mec_hal_gpio_set_props(pin_num, icfg_props_init, ARRAY_SIZE(icfg_props_init));
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if (ret) {
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return -EIO;
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}
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idet_curr = MEC_GPIO_PROP_IDET_DIS;
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ret = mec_hal_gpio_get_property(pin_num, MEC_GPIO_IDET_PROP_ID, &idet_curr);
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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idet = gen_gpio_ctrl_icfg(mode, trig);
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if (idet_curr == idet) {
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gpio_mec5_intr_en(port_num, pin, mode);
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return 0;
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}
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ret = mec_hal_gpio_set_property(pin_num, MEC_GPIO_IDET_PROP_ID, idet);
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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ret = mec_hal_gpio_pin_ia_status_clr(pin_num);
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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gpio_mec5_intr_en(port_num, pin, mode);
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return 0;
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}
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static int gpio_mec5_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value)
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{
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const struct gpio_mec5_config *config = dev->config;
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uint32_t port_num = mec5_addr_to_port(config->pcr1_base);
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int ret = mec_hal_gpio_parout_port_mask(port_num, value, (const uint32_t)mask);
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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return 0;
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}
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static int gpio_mec5_port_set_bits_raw(const struct device *dev, uint32_t mask)
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{
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const struct gpio_mec5_config *config = dev->config;
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uint32_t port_num = mec5_addr_to_port(config->pcr1_base);
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int ret = mec_hal_gpio_parout_port_set_bits(port_num, (const uint32_t)mask);
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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return 0;
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}
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static int gpio_mec5_port_clear_bits_raw(const struct device *dev, uint32_t mask)
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{
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const struct gpio_mec5_config *config = dev->config;
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uint32_t port_num = mec5_addr_to_port(config->pcr1_base);
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int ret = mec_hal_gpio_parout_port_mask(port_num, 0u, (const uint32_t)mask);
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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return 0;
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}
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static int gpio_mec5_port_toggle_bits(const struct device *dev, uint32_t mask)
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{
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const struct gpio_mec5_config *config = dev->config;
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uint32_t port_num = mec5_addr_to_port(config->pcr1_base);
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if (mec_hal_gpio_parout_port_xor(port_num, mask) != MEC_RET_OK) {
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return -EIO;
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}
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return 0;
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}
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static int gpio_mec5_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_mec5_config *config = dev->config;
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uint32_t port_num = mec5_addr_to_port(config->pcr1_base);
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if (mec_hal_gpio_parin_port(port_num, value) != MEC_RET_OK) {
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return -EIO;
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}
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return 0;
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}
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static int gpio_mec5_manage_callback(const struct device *dev, struct gpio_callback *callback,
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bool set)
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{
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struct gpio_mec5_data *data = dev->data;
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gpio_manage_callback(&data->callbacks, callback, set);
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return 0;
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}
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#ifdef CONFIG_GPIO_GET_DIRECTION
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static int gpio_mec5_get_direction(const struct device *port, gpio_port_pins_t map,
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gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
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{
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if (!port) {
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return -EINVAL;
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}
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const struct gpio_mec5_config *config = port->config;
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uint32_t valid_msk = 0u;
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uint32_t pin_num = 0u, port_num = 0u;
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int ret = 0;
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uint8_t pwr_gate = 0u, dir = 0u, in_pad_dis = 0u;
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port_num = mec5_addr_to_port(config->pcr1_base);
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ret = mec_hal_gpio_port_valid_mask(port_num, &valid_msk);
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if (ret != MEC_RET_OK) {
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return -EIO;
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}
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*inputs = 0u;
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*outputs = 0u;
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for (uint8_t pin_pos = 0; pin_pos < 32; pin++) {
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if (!map) {
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break;
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}
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if ((map & BIT(pin_pos)) && (valid_msk & BIT(pin_pos))) {
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mec_hal_gpio_pin_num(port_num, pin, &pin_num);
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mec_hal_gpio_get_property(pin_num, MEC_GPIO_PWRGT_PROP_ID, &pwr_gate);
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mec_hal_gpio_get_property(pin_num, MEC_GPIO_DIR_PROP_ID, &dir);
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mec_hal_gpio_get_property(pin_num, MEC_GPIO_INPAD_DIS_PROP_ID, &in_pad_dis);
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if (pwr_gate != MEC_GPIO_PROP_PWRGT_OFF) {
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if (outputs && (dir == MEC_GPIO_PROP_DIR_OUT)) {
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*outputs |= BIT(pin_pos);
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} else if (inputs && (in_pad_dis == MEC_GPIO_PROP_INPAD_EN)) {
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*inputs |= BIT(pin_pos);
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}
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}
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map &= ~BIT(pin_pos);
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}
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_GPIO_GET_CONFIG
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int gpio_mec5_get_config(const struct device *port, gpio_pin_t pin, gpio_flags_t *flags)
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{
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if (!port || !flags) {
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return -EINVAL;
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}
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const struct gpio_mec5_config *config = port->config;
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uint32_t port_num = mec5_addr_to_port(config->pcr1_base);
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int ret = mec_hal_gpio_port_pin_valid(port_num, pin);
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if (ret != MEC_RET_OK) {
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return -EINVAL;
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}
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uint32_t pin_ctrl = mec_hal_gpio_port_get_ctrl_nc(port_num, pin);
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uint32_t pin_flags = 0u;
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uint8_t prop = MEC_GPIO_PROP_DIR_IN;
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mec_hal_gpio_get_ctrl_property(pin_ctrl, MEC_GPIO_DIR_PROP_ID, &prop);
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if (prop == MEC_GPIO_PROP_DIR_OUT) {
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pin_flags |= GPIO_OUTPUT;
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mec_hal_gpio_get_ctrl_property(pin_ctrl, MEC_GPIO_CTRL_OUT_VAL_ID, &prop);
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if (prop != 0) {
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pin_flags |= GPIO_OUTPUT_INIT_HIGH;
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} else {
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pin_flags |= GPIO_OUTPUT_INIT_LOW;
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}
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prop = MEC_GPIO_PROP_PUSH_PULL;
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mec_hal_gpio_get_ctrl_property(pin_ctrl, MEC_GPIO_OBUFT_PROP_ID, &prop);
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if (prop == MEC_GPIO_PROP_OPEN_DRAIN) {
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pin_flags |= GPIO_OPEN_DRAIN;
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}
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} else {
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prop = MEC_GPIO_PROP_INPAD_DIS;
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mec_hal_gpio_get_ctrl_property(pin_ctrl, MEC_GPIO_INPAD_DIS_PROP_ID, &prop);
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if (prop == MEC_GPIO_PROP_INPAD_EN) {
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pin_flags |= GPIO_INPUT;
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}
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}
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if (pin_flags) {
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*flags = pin_flags;
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} else {
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*flags = GPIO_DISCONNECTED;
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}
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return 0;
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}
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#endif
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static void gpio_mec5_port_isr(const struct device *dev)
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{
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const struct gpio_mec5_config *config = dev->config;
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struct gpio_mec5_data *data = dev->data;
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uint32_t girq_result = 0xffffffffu;
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uint32_t port_num = 0u;
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/* Figure out which interrupts have been triggered from the EC
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* aggregator result register
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*/
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port_num = mec5_addr_to_port(config->pcr1_base);
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mec_hal_gpio_port_ia_result(port_num, &girq_result);
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|
|
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/* Clear source register in aggregator before firing callbacks */
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mec_hal_gpio_port_ia_status_clr_mask(port_num, girq_result);
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|
|
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gpio_fire_callbacks(&data->callbacks, dev, girq_result);
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}
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|
|
|
/* GPIO driver official API table */
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static const struct gpio_driver_api gpio_mec5_driver_api = {
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.pin_configure = gpio_mec5_configure,
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|
.port_get_raw = gpio_mec5_port_get_raw,
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|
.port_set_masked_raw = gpio_mec5_port_set_masked_raw,
|
|
.port_set_bits_raw = gpio_mec5_port_set_bits_raw,
|
|
.port_clear_bits_raw = gpio_mec5_port_clear_bits_raw,
|
|
.port_toggle_bits = gpio_mec5_port_toggle_bits,
|
|
.pin_interrupt_configure = gpio_mec5_pin_interrupt_configure,
|
|
.manage_callback = gpio_mec5_manage_callback,
|
|
#ifdef CONFIG_GPIO_GET_DIRECTION
|
|
.port_get_direction = gpio_mec5_get_direction,
|
|
#endif
|
|
#ifdef CONFIG_GPIO_GET_CONFIG
|
|
.pin_get_config = gpio_mec5_get_config,
|
|
#endif
|
|
};
|
|
|
|
#define MEC5_GPIO_PORT_FLAGS(n) ((DT_INST_IRQ_HAS_CELL(n, irq)) ? GPIO_INT_ENABLE : 0)
|
|
|
|
/* TODO remove port_num. Derive it from pin & pin_num? */
|
|
#define MEC5_GPIO_PORT(n) \
|
|
static int gpio_mec5_port_init_##n(const struct device *dev) \
|
|
{ \
|
|
if (!(DT_INST_IRQ_HAS_CELL(n, irq))) { \
|
|
return 0; \
|
|
} \
|
|
\
|
|
const struct gpio_mec5_config *config = dev->config; \
|
|
uint32_t port_num = mec5_addr_to_port(config->pcr1_base); \
|
|
\
|
|
mec_hal_gpio_port_ia_ctrl(port_num, 1u); \
|
|
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), gpio_mec5_port_isr, \
|
|
DEVICE_DT_INST_GET(n), 0u); \
|
|
irq_enable(DT_INST_IRQN(n)); \
|
|
return 0; \
|
|
} \
|
|
static struct gpio_mec5_data gpio_mec5_port_data_##n; \
|
|
static const struct gpio_mec5_config gpio_mec5_config_##n = { \
|
|
.common = \
|
|
{ \
|
|
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
|
|
}, \
|
|
.pcr1_base = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 0), \
|
|
.parin_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 1), \
|
|
.parout_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 2), \
|
|
.flags = MEC5_GPIO_PORT_FLAGS(n), \
|
|
}; \
|
|
DEVICE_DT_INST_DEFINE(n, gpio_mec5_port_init_##n, NULL, &gpio_mec5_port_data_##n, \
|
|
&gpio_mec5_config_##n, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
|
|
&gpio_mec5_driver_api);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(MEC5_GPIO_PORT)
|