03fa6a0c33
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The HAS_MCUX_XBARA is replaced by the DT_HAS_NXP_MCUX_XBAR_ENABLED Signed-off-by: Adrian Bieri <adrian.bieri@loepfe.com>
126 lines
3 KiB
Text
126 lines
3 KiB
Text
# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_IMXRT10XX
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select CPU_CORTEX_M7
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ICACHE
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select CPU_HAS_DCACHE
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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select ARM
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select CLOCK_CONTROL
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_12B1MSPS_SAR if !SOC_MIMXRT1042
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select HAS_MCUX_CCM if !SOC_MIMXRT1042
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select HAS_MCUX_FLEXSPI
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPI2C if !SOC_MIMXRT1042
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select HAS_MCUX_LPSPI if !SOC_MIMXRT1042
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select HAS_MCUX_LPUART if !SOC_MIMXRT1042
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select HAS_MCUX_GPT if !SOC_MIMXRT1042
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select HAS_MCUX_TRNG if !SOC_MIMXRT1042
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select HAS_MCUX_EDMA
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select HAS_MCUX_GPC
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select HAS_MCUX_IOMUXC
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select HAS_MCUX_PMU
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select HAS_MCUX_DCDC
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select HAS_MCUX_USB_EHCI
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select HAS_SWO
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select HAS_PM
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select SOC_RESET_HOOK
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select SOC_EARLY_INIT_HOOK
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config SOC_MIMXRT1011
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ICACHE
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select CPU_HAS_DCACHE
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select INIT_ENET_PLL
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config SOC_MIMXRT1015
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select CPU_HAS_FPU
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select CPU_HAS_ARM_MPU
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select INIT_ENET_PLL
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config SOC_MIMXRT1021
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select HAS_MCUX_ENET
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select HAS_MCUX_SEMC
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select CPU_HAS_ARM_MPU
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select INIT_ENET_PLL
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_FLEXCAN
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select HAS_MCUX_PWM
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config SOC_MIMXRT1024
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select HAS_MCUX_ENET
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select HAS_MCUX_SEMC
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select CPU_HAS_ARM_MPU
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select INIT_ENET_PLL
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_FLEXCAN
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select HAS_MCUX_SRC
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config SOC_MIMXRT1042
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select HAS_MCUX_SEMC
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select CPU_HAS_ARM_MPU
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select INIT_ARM_PLL
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select INIT_SYS_PLL
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config SOC_MIMXRT1052
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select HAS_MCUX_ELCDIF
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select HAS_MCUX_ENET
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select HAS_MCUX_SEMC
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select CPU_HAS_ARM_MPU
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select INIT_ARM_PLL
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select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
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select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_FLEXCAN
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select HAS_MCUX_PWM
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select HAS_MCUX_SRC
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config SOC_MIMXRT1062
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select HAS_MCUX_ELCDIF
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select HAS_MCUX_ENET
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select HAS_MCUX_PWM
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select HAS_MCUX_QTMR
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select HAS_MCUX_SEMC
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select HAS_MCUX_SNVS
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select CPU_HAS_ARM_MPU
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select INIT_ARM_PLL
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select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
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select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_FLEXCAN
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select HAS_MCUX_I2S
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select HAS_MCUX_ADC_ETC
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select HAS_MCUX_SRC
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config SOC_MIMXRT1064
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select HAS_MCUX_ELCDIF
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select HAS_MCUX_ENET
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select HAS_MCUX_PWM
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select HAS_MCUX_QTMR
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select HAS_MCUX_SEMC
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select HAS_MCUX_SNVS
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select HAS_MCUX_SRC
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select CPU_HAS_ARM_MPU
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select INIT_ARM_PLL
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select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
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select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_FLEXCAN
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select HAS_SWO
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