03fa6a0c33
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The HAS_MCUX_XBARA is replaced by the DT_HAS_NXP_MCUX_XBAR_ENABLED Signed-off-by: Adrian Bieri <adrian.bieri@loepfe.com>
76 lines
1.7 KiB
Text
76 lines
1.7 KiB
Text
# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_IMXRT11XX
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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select CPU_CORTEX_M_HAS_DWT
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select SOC_RESET_HOOK
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select ARM
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select CLOCK_CONTROL
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select HAS_MCUX_CACHE
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select HAS_MCUX
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select HAS_MCUX_SEMC
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select HAS_MCUX_CCM_REV2
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPI2C
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select HAS_MCUX_LPSPI
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select HAS_MCUX_LPADC
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select HAS_MCUX_ADC_ETC
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select HAS_MCUX_LPUART
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select HAS_MCUX_ELCDIF
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select HAS_MCUX_MIPI_DSI
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select HAS_MCUX_GPT
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select HAS_MCUX_FLEXSPI
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select HAS_MCUX_FLEXCAN
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select CPU_HAS_ARM_MPU
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select INIT_ARM_PLL
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select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
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select INIT_VIDEO_PLL
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select HAS_MCUX_EDMA
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select CPU_HAS_ICACHE if CPU_CORTEX_M7
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select CPU_HAS_DCACHE if CPU_CORTEX_M7
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select CPU_HAS_FPU
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select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7
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select BYPASS_LDO_LPSR
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select ADJUST_LDO
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select HAS_MCUX_PWM
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_ENET
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select HAS_MCUX_GPC
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select HAS_MCUX_I2S
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select HAS_MCUX_USB_EHCI
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select HAS_MCUX_SRC_V2
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select HAS_MCUX_IOMUXC
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select HAS_SWO
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select HAS_PM
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config SOC_MIMXRT1176_CM4
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select CPU_CORTEX_M4
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config SOC_MIMXRT1176_CM7
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select CPU_CORTEX_M7
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config SOC_MIMXRT1166_CM4
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select CPU_CORTEX_M4
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config SOC_MIMXRT1166_CM7
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select CPU_CORTEX_M7
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if SOC_SERIES_IMXRT11XX
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config MCUX_CORE_SUFFIX
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default "_cm7" if SOC_MIMXRT1176_CM7 || SOC_MIMXRT1166_CM7
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default "_cm4" if SOC_MIMXRT1176_CM4 || SOC_MIMXRT1166_CM4
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config BYPASS_LDO_LPSR
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bool "Bypass LDO lpsr"
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config ADJUST_LDO
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bool "Adjust LDO setting"
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config ADJUST_DCDC
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default y
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bool "Adjust internal DCDC output"
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endif # SOC_SERIES_IMXRT11XX
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