180cdc105e
Up until now, the Zephyr CAN controller drivers set a default bitrate (or timing) specified via devicetree and start the CAN controller in their respective driver initialization functions. This is fine for CAN nodes using only one fixed bitrate, but if the bitrate is set by the user (e.g. via a DIP-switch or other HMI which is very common), the CAN driver will still initialise with the default bitrate/timing at boot and use this until the application has determined the requested bitrate/timing and set it using can_set_bitrate()/can_set_timing(). During this period, the CAN node will potentially destroy valid CAN frames on the CAN bus (which is using the soon-to-be-set-by-the-application bitrate) by sending error frames. This causes interruptions to the ongoing CAN bus traffic when a Zephyr-based CAN node connected to the bus is (re-)booted. Instead, require all configuration (setting bitrate, timing, or mode) to take place when the CAN controller is stopped. This maps nicely to entering "reset mode" (called "configuration mode" or "freeze mode" for some CAN controller implementations) when stopping and exiting this mode when starting the CAN controller. Fixes: #45304 Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
168 lines
5.1 KiB
C
168 lines
5.1 KiB
C
/*
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* Copyright (c) 2022 Vestas Wind Systems A/S
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* Copyright (c) 2021 Alexander Wachter
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/can.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include "can_mcan.h"
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LOG_MODULE_REGISTER(can_sam, CONFIG_CAN_LOG_LEVEL);
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#define DT_DRV_COMPAT atmel_sam_can
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struct can_sam_config {
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void (*config_irq)(void);
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const struct pinctrl_dev_config *pcfg;
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uint8_t pmc_id;
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int divider;
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};
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struct can_sam_data {
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struct can_mcan_msg_sram msg_ram;
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};
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static int can_sam_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_sam_config *sam_cfg = mcan_cfg->custom;
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*rate = SOC_ATMEL_SAM_UPLLCK_FREQ_HZ / (sam_cfg->divider);
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return 0;
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}
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static void can_sam_clock_enable(const struct can_sam_config *sam_cfg)
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{
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REG_PMC_PCK5 = PMC_PCK_CSS_UPLL_CLK | PMC_PCK_PRES(sam_cfg->divider - 1);
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PMC->PMC_SCER |= PMC_SCER_PCK5;
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soc_pmc_peripheral_enable(sam_cfg->pmc_id);
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}
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static int can_sam_init(const struct device *dev)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_sam_config *sam_cfg = mcan_cfg->custom;
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int ret;
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can_sam_clock_enable(sam_cfg);
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ret = pinctrl_apply_state(sam_cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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ret = can_mcan_init(dev);
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if (ret != 0) {
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return ret;
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}
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sam_cfg->config_irq();
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return ret;
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}
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static const struct can_driver_api can_sam_driver_api = {
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.get_capabilities = can_mcan_get_capabilities,
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.start = can_mcan_start,
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.stop = can_mcan_stop,
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.set_mode = can_mcan_set_mode,
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.set_timing = can_mcan_set_timing,
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.send = can_mcan_send,
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.add_rx_filter = can_mcan_add_rx_filter,
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.remove_rx_filter = can_mcan_remove_rx_filter,
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.get_state = can_mcan_get_state,
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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.recover = can_mcan_recover,
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#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
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.get_core_clock = can_sam_get_core_clock,
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.get_max_filters = can_mcan_get_max_filters,
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.get_max_bitrate = can_mcan_get_max_bitrate,
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.set_state_change_callback = can_mcan_set_state_change_callback,
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.timing_min = {
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.sjw = 0x1,
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.prop_seg = 0x00,
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.phase_seg1 = 0x01,
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.phase_seg2 = 0x01,
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.prescaler = 0x01
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},
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.timing_max = {
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.sjw = 0x7f,
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.prop_seg = 0x00,
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.phase_seg1 = 0x100,
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.phase_seg2 = 0x80,
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.prescaler = 0x200
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},
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#ifdef CONFIG_CAN_FD_MODE
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.set_timing_data = can_mcan_set_timing_data,
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.timing_data_min = {
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.sjw = 0x01,
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.prop_seg = 0x00,
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.phase_seg1 = 0x01,
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.phase_seg2 = 0x01,
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.prescaler = 0x01
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},
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.timing_data_max = {
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.sjw = 0x10,
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.prop_seg = 0x00,
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.phase_seg1 = 0x20,
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.phase_seg2 = 0x10,
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.prescaler = 0x20
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}
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#endif /* CONFIG_CAN_FD_MODE */
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};
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#define CAN_SAM_IRQ_CFG_FUNCTION(inst) \
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static void config_can_##inst##_irq(void) \
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{ \
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LOG_DBG("Enable CAN##inst## IRQ"); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_0, irq), \
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DT_INST_IRQ_BY_NAME(inst, line_0, priority), can_mcan_line_0_isr, \
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DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(inst, line_0, irq)); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_1, irq), \
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DT_INST_IRQ_BY_NAME(inst, line_1, priority), can_mcan_line_1_isr, \
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DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(inst, line_1, irq)); \
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}
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#define CAN_SAM_CFG_INST(inst) \
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static const struct can_sam_config can_sam_cfg_##inst = { \
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.pmc_id = DT_INST_PROP(inst, peripheral_id), \
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.divider = DT_INST_PROP(inst, divider), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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.config_irq = config_can_##inst##_irq, \
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}; \
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\
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static const struct can_mcan_config can_mcan_cfg_##inst = \
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CAN_MCAN_DT_CONFIG_INST_GET(inst, &can_sam_cfg_##inst);
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#define CAN_SAM_DATA_INST(inst) \
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static struct can_sam_data can_sam_data_##inst; \
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\
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static struct can_mcan_data can_mcan_data_##inst = \
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CAN_MCAN_DATA_INITIALIZER(&can_sam_data_##inst.msg_ram, \
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&can_sam_data_##inst); \
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#define CAN_SAM_DEVICE_INST(inst) \
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DEVICE_DT_INST_DEFINE(inst, &can_sam_init, NULL, \
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&can_mcan_data_##inst, \
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&can_mcan_cfg_##inst, \
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POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
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&can_sam_driver_api);
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#define CAN_SAM_INST(inst) \
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PINCTRL_DT_INST_DEFINE(inst); \
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CAN_SAM_IRQ_CFG_FUNCTION(inst) \
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CAN_SAM_CFG_INST(inst) \
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CAN_SAM_DATA_INST(inst) \
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CAN_SAM_DEVICE_INST(inst)
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DT_INST_FOREACH_STATUS_OKAY(CAN_SAM_INST)
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