1a1a9539ea
Rename timer driver API functions to be consistent. ADD DOCS TO THE HEADER so implementations understand what the requirements are. Remove some unused functions that don't need declarations here. Also removes the per-platform #if's around the power control callback in favor of a weak-linked noop function in the driver initialization (adds a few bytes of code to default platforms -- we'll live, I think). Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
117 lines
2.9 KiB
C
117 lines
2.9 KiB
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <device.h>
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#include <system_timer.h>
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#include <board.h>
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#include "legacy_api.h"
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typedef struct {
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u32_t val_low;
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u32_t val_high;
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} riscv_machine_timer_t;
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static volatile riscv_machine_timer_t *mtime =
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(riscv_machine_timer_t *)RISCV_MTIME_BASE;
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static volatile riscv_machine_timer_t *mtimecmp =
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(riscv_machine_timer_t *)RISCV_MTIMECMP_BASE;
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/*
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* The RISCV machine-mode timer is a one shot timer that needs to be rearm upon
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* every interrupt. Timer clock is a 64-bits ART.
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* To arm timer, we need to read the RTC value and update the
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* timer compare register by the RTC value + time interval we want timer
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* to interrupt.
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*/
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static ALWAYS_INLINE void riscv_machine_rearm_timer(void)
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{
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u64_t rtc;
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/*
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* Disable timer interrupt while rearming the timer
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* to avoid generation of interrupts while setting
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* the mtimecmp->val_low register.
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*/
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irq_disable(RISCV_MACHINE_TIMER_IRQ);
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/*
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* Following machine-mode timer implementation in QEMU, the actual
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* RTC read is performed when reading low timer value register.
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* Reading high timer value just reads the most significant 32-bits
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* of a cache value, obtained from a previous read to the low
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* timer value register. Hence, always read timer->val_low first.
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* This also works for other implementations.
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*/
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rtc = mtime->val_low;
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rtc |= ((u64_t)mtime->val_high << 32);
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/*
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* Rearm timer to generate an interrupt after
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* sys_clock_hw_cycles_per_tick()
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*/
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rtc += sys_clock_hw_cycles_per_tick();
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mtimecmp->val_low = (u32_t)(rtc & 0xffffffff);
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mtimecmp->val_high = (u32_t)((rtc >> 32) & 0xffffffff);
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/* Enable timer interrupt */
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irq_enable(RISCV_MACHINE_TIMER_IRQ);
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}
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static void riscv_machine_timer_irq_handler(void *unused)
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{
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ARG_UNUSED(unused);
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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extern void read_timer_start_of_tick_handler(void);
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read_timer_start_of_tick_handler();
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#endif
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z_clock_announce(1);
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/* Rearm timer */
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riscv_machine_rearm_timer();
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#ifdef CONFIG_EXECUTION_BENCHMARKING
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extern void read_timer_end_of_tick_handler(void);
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read_timer_end_of_tick_handler();
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#endif
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}
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#ifdef CONFIG_TICKLESS_IDLE
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#error "Tickless idle not yet implemented for riscv-machine timer"
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#endif
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int z_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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IRQ_CONNECT(RISCV_MACHINE_TIMER_IRQ, 0,
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riscv_machine_timer_irq_handler, NULL, 0);
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/* Initialize timer, just call riscv_machine_rearm_timer */
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riscv_machine_rearm_timer();
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return 0;
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}
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/**
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*
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* @brief Read the platform's timer hardware
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*
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* This routine returns the current time in terms of timer hardware clock
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* cycles.
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*
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* @return up counter of elapsed clock cycles
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*/
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u32_t _timer_cycle_get_32(void)
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{
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/* We just want a cycle count so just post what's in the low 32
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* bits of the mtime real-time counter
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*/
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return mtime->val_low;
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}
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