1e75491cdb
The exit latency and min residency is handled by sl_power_manager. This improve power consumption by letting the device sleep longer. Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
382 lines
8.3 KiB
Text
382 lines
8.3 KiB
Text
/*
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* Copyright (c) 2021 Sateesh Kotapati
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/pinctrl/gecko-pinctrl.h>
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#include <dt-bindings/adc/adc.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &msc;
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zephyr,entropy = &trng;
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};
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clocks {
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sysclk: sysclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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hclk: hclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sysclk>;
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/* Divisors 1, 2, 4, 8, 16 allowed */
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clock-div = <1>;
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};
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pclk: pclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hclk>;
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/* Divisors 1, 2 allowed */
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clock-div = <2>;
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};
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lspclk: lspclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&pclk>;
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/* Fixed divisor of 2 */
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clock-div = <2>;
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};
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hclkdiv1024: hclkdiv1024 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hclk>;
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/* Fixed divisor of 1024 */
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clock-div = <1024>;
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};
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traceclk: traceclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sysclk>;
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/* Divisors 1, 2, 3, 4 allowed */
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clock-div = <1>;
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};
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em01grpaclk: em01grpaclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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em01grpbclk: em01grpbclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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iadcclk: iadcclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&em01grpaclk>;
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};
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em23grpaclk: em23grpaclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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em4grpaclk: em4grpaclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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rtccclk: rtccclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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wdog0clk: wdog0clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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systickclk: systickclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hclk>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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/*
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* EM1 is enabled by default because it is
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* unconditionally safe.
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*
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* EM2/3 can be enabled by the board code if proper
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* timing configuration is ensured:
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* - for EM2, EM3: BURTC used as sys_clock
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* - for EM3: BURTC clocked from ULFRCO
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* Using BURTC as sys_clock instead of SysTick
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* has implications on system performance. Read
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* KConfig documentation entry before enabling it.
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*
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* The minimum residency and exit latency is
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* managed by sl_power_manager on S2 devices.
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*/
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cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
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};
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power-states {
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/*
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* EM1 is a basic "CPU WFI idle", all high-freq clocks remain
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* enabled.
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*/
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pstate_em1: em1 {
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compatible = "zephyr,power-state";
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power-state-name = "runtime-idle";
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/* HFXO remains active */
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};
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/*
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* EM2 is a deepsleep with HF clocks disabled by HW, voltages
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* scaled down, etc.
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*/
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pstate_em2: em2 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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};
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/*
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* EM3 seems to be exactly the same as EM2 except that
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* LFXO & LFRCO should be disabled, so you must use ULFRCO
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* as BURTC clock for the system to not lose track of time and
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* wake up.
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*/
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pstate_em3: em3 {
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compatible = "zephyr,power-state";
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power-state-name = "standby";
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};
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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soc {
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cmu: clock@50008000 {
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compatible = "silabs,series-clock";
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reg = <0x50008000 0x4000>;
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interrupt-names = "cmu";
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status = "okay";
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#clock-cells = <2>;
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};
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fsrco: fsrco@50018000 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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reg = <0x50018000 0x4000>;
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clock-frequency = <DT_FREQ_M(20)>;
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};
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clk_hfxo: hfxo: hfxo@5000c000 {
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#clock-cells = <0>;
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compatible = "silabs,hfxo";
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reg = <0x5000c000 0x4000>;
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clock-frequency = <DT_FREQ_K(38400)>;
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ctune = <140>;
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precision = <50>;
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status = "disabled";
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};
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lfxo: lfxo@50020000 {
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#clock-cells = <0>;
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compatible = "silabs,series2-lfxo";
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reg = <0x50020000 0x4000>;
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clock-frequency = <32768>;
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ctune = <63>;
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precision = <50>;
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timeout = <4096>;
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status = "disabled";
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};
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hfrcodpll: hfrcodpll@50010000 {
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#clock-cells = <0>;
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compatible = "silabs,series2-hfrcodpll";
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reg = <0x50010000 0x4000>;
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clock-frequency = <DT_FREQ_M(19)>;
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};
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lfrco: lfrco@50024000 {
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#clock-cells = <0>;
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compatible = "silabs,series2-lfrco";
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reg = <0x50024000 0x4000>;
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clock-frequency = <32768>;
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};
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ulfrco: ulfrco@50028000 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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reg = <0x50028000 0x4000>;
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clock-frequency = <1000>;
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};
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msc: flash-controller@50030000 {
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compatible = "silabs,gecko-flash-controller";
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reg = <0x50030000 0xC69>;
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interrupts = <49 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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usart0: usart@5005c000 {
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compatible = "silabs,usart-spi";
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reg = <0x5005C000 0x400>;
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interrupt-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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usart1: usart@50060000 {
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compatible = "silabs,usart-uart";
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reg = <0x50060000 0x400>;
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interrupt-names = "rx", "tx";
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status = "disabled";
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};
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burtc0: burtc@50064000 {
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compatible = "silabs,gecko-burtc";
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reg = <0x50064000 0x3034>;
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status = "disabled";
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};
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rtcc0: stimer0: rtcc@58000000 {
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compatible = "silabs,gecko-stimer";
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reg = <0x58000000 0x3054>;
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clock-frequency = <32768>;
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prescaler = <1>;
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status = "disabled";
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};
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trng: trng@4c021000 {
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compatible = "silabs,gecko-trng";
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reg = <0x4C021000 0x1000>;
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status = "disabled";
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interrupts = <0x1 0x0>;
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};
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i2c0: i2c@5a010000 {
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compatible = "silabs,gecko-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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reg = <0x5a010000 0x3044>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@50068000 {
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compatible = "silabs,gecko-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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reg = <0x50068000 0x3044>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gpio: gpio@5003c000 {
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compatible = "silabs,gecko-gpio";
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reg = <0x5003C000 0x440>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@5003c000 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003C000 0x30>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiob: gpio@5003c030 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003C030 0x30>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpioc: gpio@5003c060 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003C060 0x30>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiod: gpio@5003c090 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003C090 0x30>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiof: gpio@5003c0c0 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003C0C0 0x30>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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};
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pinctrl: pin-controller@5003c440 {
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compatible = "silabs,dbus-pinctrl";
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reg = <0x5003c440 0xbc0>;
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};
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dma0: dma@40040000{
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compatible = "silabs,ldma";
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reg = <0x40040000 0x4000>;
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#dma-cells = <3>;
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dma_channels = <8>;
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status = "disabled";
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};
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wdog0: wdog@4a018000 {
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compatible = "silabs,gecko-wdog";
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reg = <0x4A018000 0x3028>;
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peripheral-id = <0>;
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interrupts = <43 0>;
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status = "disabled";
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};
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adc0: adc@5a004000 {
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compatible = "silabs,gecko-iadc";
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reg = <0x5a004000 0x4000>;
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interrupts = <48 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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dcdc: dcdc@50094000 {
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compatible = "silabs,series2-dcdc";
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reg = <0x50094000 0x4000>;
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status = "disabled";
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};
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};
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bt_hci_silabs: bt_hci_silabs {
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compatible = "silabs,bt-hci-efr32";
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status = "disabled";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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