On Arm Cortex R52, cache segregation policy controls the number of L1 I/D cache ways that are allocated to Flash and AXIM interface. Adding Kconfig options for configuring it. Writing to IMP_CSCTRL is only permitted before the caches have been enabled, following a system reset. Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com> |
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| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| common | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| archs.yml | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.v1 | ||
| Kconfig.v2 | ||