Santosh Male 3e0b068fff SOC: Updated MAX IRQ num supported by Aglex5 ... Agilex5 device supports maximum of 274 interrupts which includes XMAC interrupts as well. Signed-off-by: Santosh Male <santosh.male@intel.com>		2024-09-05 17:03:05 -04:00
..
alder_lake	soc: x86: add gpio acpi resource enumeration	2024-04-22 06:50:38 -07:00
apollo_lake	drivers/timer/apic_tsc: use ICR as a fallback timeout event source	2024-05-29 08:40:43 +02:00
atom
common	soc: x86: add gpio acpi resource enumeration	2024-04-22 06:50:38 -07:00
elkhart_lake
intel_adsp	soc: intel_adsp: ace: Configurable SRAM retention mode and cleanup	2024-09-05 16:56:56 -04:00
intel_ish	soc: intel_ish: Make ISH support APIC timer with TSC time source.	2024-06-12 17:10:25 -05:00
intel_niosv	arch: riscv: imply XIP config pushed to SoC level	2024-08-31 06:47:52 -04:00
intel_socfpga	SOC: Updated MAX IRQ num supported by Aglex5	2024-09-05 17:03:05 -04:00
intel_socfpga_std	soc: intel_socfpga_std/cyclonev: enforce ARM_AARCH32_MMU	2024-07-05 18:39:53 +02:00
lakemont
raptor_lake	soc: x86: add gpio acpi resource enumeration	2024-04-22 06:50:38 -07:00