36e71c839f
The clock controller/manager registers are updated with the correct divider values by bootloader via hand-off data, so now we can use the clock controller to get the clock value of each peripheral during the run time. Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
46 lines
1.6 KiB
C
46 lines
1.6 KiB
C
/*
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* Copyright (c) 2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/cpu.h>
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#include <zephyr/arch/arm64/arm_mmu.h>
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static const struct arm_mmu_region mmu_regions[] = {
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MMU_REGION_FLAT_ENTRY("CLOCK",
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DT_REG_ADDR(DT_NODELABEL(clock)),
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DT_REG_SIZE(DT_NODELABEL(clock)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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/* System manager register that required by clock driver */
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MMU_REGION_FLAT_ENTRY("SYSTEM_MANAGER",
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DT_REG_ADDR(DT_NODELABEL(sysmgr)),
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DT_REG_SIZE(DT_NODELABEL(sysmgr)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
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MMU_REGION_FLAT_ENTRY("PINMUX",
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DT_REG_ADDR_BY_IDX(DT_NODELABEL(pinmux), 0),
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DT_REG_SIZE_BY_IDX(DT_NODELABEL(pinmux), 0),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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MMU_REGION_FLAT_ENTRY("GIC_0",
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DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
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DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
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MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
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MMU_REGION_FLAT_ENTRY("GIC_1",
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DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
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DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
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MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
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MMU_REGION_FLAT_ENTRY("GIC_ITS",
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DT_REG_ADDR(DT_NODELABEL(its)),
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DT_REG_SIZE(DT_NODELABEL(its)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
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};
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const struct arm_mmu_config mmu_config = {
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.num_regions = ARRAY_SIZE(mmu_regions),
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.mmu_regions = mmu_regions,
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};
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