88de80b774
STM32 MCU shall set voltage regulator level with respect to set clock frequency to reach optimal power consumption. Voltage regulator is set prior to clock setting based on configuration from dts/overlay file. Config_regulator_voltage is set as weak in clock_stm32_ll_common - config_regulator_voltage can be extended to other STM32 families without need to rewrite heavily family clock driver, default one can be still used. Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
62 lines
1.4 KiB
C
62 lines
1.4 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_
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#define ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_
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#include <stdint.h>
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#include <zephyr/device.h>
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#include <stm32_ll_utils.h>
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/* Macros to fill up multiplication and division factors values */
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#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
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#define pllm(v) z_pllm(v)
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#define z_pllp(v) LL_RCC_PLLP_DIV_ ## v
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#define pllp(v) z_pllp(v)
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#define z_pllq(v) LL_RCC_PLLQ_DIV_ ## v
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#define pllq(v) z_pllq(v)
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#define z_pllr(v) LL_RCC_PLLR_DIV_ ## v
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#define pllr(v) z_pllr(v)
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#define z_plli2s_m(v) LL_RCC_PLLI2SM_DIV_ ## v
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#define plli2sm(v) z_plli2s_m(v)
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#define z_plli2s_r(v) LL_RCC_PLLI2SR_DIV_ ## v
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#define plli2sr(v) z_plli2s_r(v)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(STM32_PLL_ENABLED)
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void config_pll_sysclock(void);
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uint32_t get_pllout_frequency(void);
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uint32_t get_pllsrc_frequency(void);
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#endif
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#if defined(STM32_PLL2_ENABLED)
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void config_pll2(void);
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#endif
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#if defined(STM32_PLLI2S_ENABLED)
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void config_plli2s(void);
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#endif
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void config_enable_default_clocks(void);
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void config_regulator_voltage(uint32_t hclk_freq);
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/* functions exported to the soc power.c */
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int stm32_clock_control_init(const struct device *dev);
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void stm32_clock_control_standby_exit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ */
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