5b3d4598a7
This removes all occurrences of arm,num-mpu-regions relying on the value reported by the register instead. A user may still define this property if they need to have a compile time definition for it. Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
741 lines
18 KiB
Text
741 lines
18 KiB
Text
/*
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* Copyright (c) 2021 The Chromium OS Authors
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* Copyright (c) 2020 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
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#include <zephyr/dt-bindings/dma/stm32_dma.h>
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#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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#include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/flash_controller/ospi.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,entropy = &rng;
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpu-power-states = <&stop0 &stop1 &stop2>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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power-states {
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stop0: state0 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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substate-id = <1>;
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min-residency-us = <100>;
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};
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stop1: state1 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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substate-id = <2>;
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min-residency-us = <500>;
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};
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stop2: state2 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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substate-id = <3>;
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min-residency-us = <900>;
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};
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(16)>;
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status = "disabled";
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};
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clk_hsi48: clk-hsi48 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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status = "disabled";
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};
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clk_msi: clk-msi {
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#clock-cells = <0>;
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compatible = "st,stm32-msi-clock";
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msi-range = <6>; /* 4MHz (reset value) */
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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clock-frequency = <32768>;
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driving-capability = <0>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32l4-pll-clock";
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller";
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reg = <0x40022000 0x400>;
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interrupts = <6 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <8>;
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erase-block-size = <2048>;
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/* using maximum erase time(ms) for 4K page, since
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* datasheet does not show the maximum erase
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* for a 2K(dual-bank) page.
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*/
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max-erase-time = <25>;
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};
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};
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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clocks-controller;
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#clock-cells = <2>;
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reg = <0x40021000 0x400>;
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undershoot-prevention;
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rctl: reset-controller {
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compatible = "st,stm32-rcc-rctl";
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#reset-cells = <1>;
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};
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};
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exti: interrupt-controller@4000f400 {
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compatible = "st,stm32g0-exti", "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x4000f400 0x400>;
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num-lines = <16>;
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interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
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<15 0>, <16 0>, <17 0>, <18 0>,
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<19 0>, <20 0>, <21 0>, <22 0>,
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<23 0>, <24 0>, <25 0>, <26 0>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5", "line6", "line7",
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"line8", "line9", "line10", "line11",
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"line12", "line13", "line14", "line15";
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line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
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<4 1>, <5 1>, <6 1>, <7 1>,
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<8 1>, <9 1>, <10 1>, <11 1>,
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<12 1>, <13 1>, <14 1>, <15 1>;
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};
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pinctrl: pin-controller@42020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x42020000 0x2000>;
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gpioa: gpio@42020000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
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};
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gpiob: gpio@42020400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
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};
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gpioc: gpio@42020800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
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};
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gpiod: gpio@42020c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
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};
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gpioe: gpio@42021000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
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};
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gpiof: gpio@42021400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
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};
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gpiog: gpio@42021800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
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};
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gpioh: gpio@42021c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
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};
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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interrupts = <0 6>;
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status = "disabled";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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resets = <&rctl STM32_RESET(APB2, 14U)>;
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interrupts = <61 0>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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resets = <&rctl STM32_RESET(APB1L, 17U)>;
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interrupts = <62 0>;
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status = "disabled";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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resets = <&rctl STM32_RESET(APB1L, 18U)>;
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interrupts = <63 0>;
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status = "disabled";
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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resets = <&rctl STM32_RESET(APB1L, 19U)>;
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interrupts = <64 0>;
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status = "disabled";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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resets = <&rctl STM32_RESET(APB1L, 20U)>;
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interrupts = <65 0>;
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status = "disabled";
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};
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lpuart1: serial@40008000 {
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compatible = "st,stm32-lpuart", "st,stm32-uart";
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reg = <0x40008000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
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resets = <&rctl STM32_RESET(APB1H, 0U)>;
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interrupts = <66 0>;
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status = "disabled";
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};
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lptim1: timers@40007c00 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007c00 0x400>;
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interrupts = <67 1>;
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interrupt-names = "wakeup";
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status = "disabled";
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};
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dma1: dma@40020000 {
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compatible = "st,stm32-dma-v2";
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#dma-cells = <3>;
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reg = <0x40020000 0x400>;
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interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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dma-requests = <8>;
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dma-offset = <0>;
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status = "disabled";
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};
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dma2: dma@40020400 {
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compatible = "st,stm32-dma-v2";
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#dma-cells = <3>;
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reg = <0x40020400 0x400>;
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interrupts = <80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
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dma-requests = <8>;
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dma-offset = <8>;
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status = "disabled";
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};
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dmamux1: dmamux@40020800 {
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compatible = "st,stm32-dmamux";
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#dma-cells = <3>;
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reg = <0x40020800 0x400>;
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interrupts = <27 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
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dma-channels = <16>;
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dma-generators = <4>;
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dma-requests= <90>;
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status = "disabled";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <55 0>, <56 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <57 0>, <58 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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interrupts = <59 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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status = "disabled";
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};
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sdmmc1: sdmmc@420c8000 {
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compatible = "st,stm32-sdmmc";
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reg = <0x420c8000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00400000>,
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<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
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resets = <&rctl STM32_RESET(AHB2, 22U)>;
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interrupts = <78 0>;
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status = "disabled";
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};
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dac1: dac@40007400 {
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compatible = "st,stm32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <60 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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status = "disabled";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003c00 0x400>;
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interrupts = <99 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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status = "disabled";
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};
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octospi1: octospi@44021000 {
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compatible = "st,stm32-ospi";
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reg = <0x44021000 0x400>;
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interrupts = <76 0>;
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clock-names = "ospix", "ospi-ker";
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>,
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<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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rng: rng@420c0800 {
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compatible = "st,stm32-rng";
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reg = <0x420c0800 0x400>;
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interrupts = <94 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
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nist-config = <0xf00d00>;
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health-test-magic = <0x17590abc>;
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health-test-config = <0xa2b3>;
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status = "disabled";
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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interrupts = <2 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
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prescaler = <32768>;
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status = "disabled";
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};
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
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resets = <&rctl STM32_RESET(APB2, 11U)>;
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interrupts = <41 0>, <42 0>, <43 0>, <44 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers2: timers@40000000 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
|
|
resets = <&rctl STM32_RESET(APB1L, 0U)>;
|
|
interrupts = <45 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers3: timers@40000400 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
|
|
resets = <&rctl STM32_RESET(APB1L, 1U)>;
|
|
interrupts = <46 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers4: timers@40000800 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
|
resets = <&rctl STM32_RESET(APB1L, 2U)>;
|
|
interrupts = <47 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers5: timers@40000c00 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000c00 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
|
|
resets = <&rctl STM32_RESET(APB1L, 3U)>;
|
|
interrupts = <48 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers8: timers@40013400 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40013400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
|
|
resets = <&rctl STM32_RESET(APB2, 13U)>;
|
|
interrupts = <51 0>, <52 0>, <53 0>, <54 0>;
|
|
interrupt-names = "brk", "up", "trgcom", "cc";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers15: timers@40014000 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
|
|
resets = <&rctl STM32_RESET(APB2, 16U)>;
|
|
interrupts = <69 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers16: timers@40014400 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
|
|
resets = <&rctl STM32_RESET(APB2, 17U)>;
|
|
interrupts = <70 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers17: timers@40014800 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
|
|
resets = <&rctl STM32_RESET(APB2, 18U)>;
|
|
interrupts = <71 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
adc1: adc@42028000 {
|
|
compatible = "st,stm32-adc";
|
|
reg = <0x42028000 0x100>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
|
|
interrupts = <37 0>;
|
|
status = "disabled";
|
|
#io-channel-cells = <1>;
|
|
resolutions = <STM32_ADC_RES(12, 0x00)
|
|
STM32_ADC_RES(10, 0x01)
|
|
STM32_ADC_RES(8, 0x02)
|
|
STM32_ADC_RES(6, 0x03)>;
|
|
sampling-times = <3 7 13 25 48 93 248 641>;
|
|
st,adc-sequencer = <FULLY_CONFIGURABLE>;
|
|
};
|
|
|
|
adc2: adc@42028100 {
|
|
compatible = "st,stm32-adc";
|
|
reg = <0x42028100 0x100>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
|
|
interrupts = <37 0>;
|
|
status = "disabled";
|
|
#io-channel-cells = <1>;
|
|
resolutions = <STM32_ADC_RES(12, 0x00)
|
|
STM32_ADC_RES(10, 0x01)
|
|
STM32_ADC_RES(8, 0x02)
|
|
STM32_ADC_RES(6, 0x03)>;
|
|
sampling-times = <3 7 13 25 48 93 248 641>;
|
|
st,adc-sequencer = <FULLY_CONFIGURABLE>;
|
|
};
|
|
|
|
usb: usb@4000d400 {
|
|
compatible = "st,stm32-usb";
|
|
reg = <0x4000d400 0x400>;
|
|
interrupts = <73 0>;
|
|
interrupt-names = "usb";
|
|
num-bidir-endpoints = <8>;
|
|
ram-size = <1024>;
|
|
status = "disabled";
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00200000>,
|
|
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
|
|
phys = <&usb_fs_phy>;
|
|
};
|
|
|
|
ucpd1: ucpd@4000dc00 {
|
|
compatible = "st,stm32-ucpd";
|
|
reg = <0x4000dc00 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
|
|
interrupts = <106 0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
die_temp: dietemp {
|
|
compatible = "st,stm32-temp-cal";
|
|
ts-cal1-addr = <0x0BFA05A8>;
|
|
ts-cal2-addr = <0x0BFA05CA>;
|
|
ts-cal1-temp = <30>;
|
|
ts-cal2-temp = <130>;
|
|
ts-cal-vrefanalog = <3000>;
|
|
io-channels = <&adc1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vref: vref {
|
|
compatible = "st,stm32-vref";
|
|
vrefint-cal-addr = <0x0BFA05AA>;
|
|
vrefint-cal-mv = <3000>;
|
|
io-channels = <&adc1 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vbat: vbat {
|
|
compatible = "st,stm32-vbat";
|
|
ratio = <3>;
|
|
io-channels = <&adc1 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_fs_phy: usbphy {
|
|
compatible = "usb-nop-xceiv";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <3>;
|
|
};
|