6d2a42c21e
The minimum/maximum CAN timing parameters for the Atmel SAM CAN driver uses the wrong values for the minimum, nominal phase segment values. The same goes for the maximum, nominal SJW value. Using the static initializers fixes these and aligns them to both the Bosch M_CAN manual and the Atmel SAM E70 family data sheet. Fixes: #58429 Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
205 lines
6.9 KiB
C
205 lines
6.9 KiB
C
/*
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* Copyright (c) 2022 Vestas Wind Systems A/S
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* Copyright (c) 2021 Alexander Wachter
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/can.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
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#include <soc.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include "can_mcan.h"
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LOG_MODULE_REGISTER(can_sam, CONFIG_CAN_LOG_LEVEL);
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#define DT_DRV_COMPAT atmel_sam_can
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struct can_sam_config {
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mm_reg_t base;
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mem_addr_t mram;
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void (*config_irq)(void);
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const struct atmel_sam_pmc_config clock_cfg;
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const struct pinctrl_dev_config *pcfg;
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int divider;
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};
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static int can_sam_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_sam_config *sam_config = mcan_config->custom;
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return can_mcan_sys_read_reg(sam_config->base, reg, val);
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}
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static int can_sam_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_sam_config *sam_config = mcan_config->custom;
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return can_mcan_sys_write_reg(sam_config->base, reg, val);
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}
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static int can_sam_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_sam_config *sam_config = mcan_config->custom;
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return can_mcan_sys_read_mram(sam_config->mram, offset, dst, len);
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}
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static int can_sam_write_mram(const struct device *dev, uint16_t offset, const void *src,
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size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_sam_config *sam_config = mcan_config->custom;
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return can_mcan_sys_write_mram(sam_config->mram, offset, src, len);
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}
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static int can_sam_clear_mram(const struct device *dev, uint16_t offset, size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_sam_config *sam_config = mcan_config->custom;
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return can_mcan_sys_clear_mram(sam_config->mram, offset, len);
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}
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static int can_sam_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_sam_config *sam_cfg = mcan_cfg->custom;
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*rate = SOC_ATMEL_SAM_UPLLCK_FREQ_HZ / (sam_cfg->divider);
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return 0;
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}
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static void can_sam_clock_enable(const struct can_sam_config *sam_cfg)
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{
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REG_PMC_PCK5 = PMC_PCK_CSS_UPLL_CLK | PMC_PCK_PRES(sam_cfg->divider - 1);
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PMC->PMC_SCER |= PMC_SCER_PCK5;
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/* Enable CAN clock in PMC */
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(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
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(clock_control_subsys_t)&sam_cfg->clock_cfg);
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}
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static int can_sam_init(const struct device *dev)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_sam_config *sam_cfg = mcan_cfg->custom;
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int ret;
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can_sam_clock_enable(sam_cfg);
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ret = pinctrl_apply_state(sam_cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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ret = can_mcan_configure_mram(dev, 0U, sam_cfg->mram);
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if (ret != 0) {
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return ret;
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}
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ret = can_mcan_init(dev);
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if (ret != 0) {
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return ret;
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}
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sam_cfg->config_irq();
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return ret;
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}
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static const struct can_driver_api can_sam_driver_api = {
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.get_capabilities = can_mcan_get_capabilities,
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.start = can_mcan_start,
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.stop = can_mcan_stop,
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.set_mode = can_mcan_set_mode,
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.set_timing = can_mcan_set_timing,
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.send = can_mcan_send,
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.add_rx_filter = can_mcan_add_rx_filter,
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.remove_rx_filter = can_mcan_remove_rx_filter,
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.get_state = can_mcan_get_state,
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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.recover = can_mcan_recover,
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#endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
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.get_core_clock = can_sam_get_core_clock,
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.get_max_filters = can_mcan_get_max_filters,
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.get_max_bitrate = can_mcan_get_max_bitrate,
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.set_state_change_callback = can_mcan_set_state_change_callback,
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.timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
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.timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
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#ifdef CONFIG_CAN_FD_MODE
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.set_timing_data = can_mcan_set_timing_data,
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.timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
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.timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
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#endif /* CONFIG_CAN_FD_MODE */
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};
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static const struct can_mcan_ops can_sam_ops = {
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.read_reg = can_sam_read_reg,
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.write_reg = can_sam_write_reg,
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.read_mram = can_sam_read_mram,
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.write_mram = can_sam_write_mram,
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.clear_mram = can_sam_clear_mram,
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};
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#define CAN_SAM_IRQ_CFG_FUNCTION(inst) \
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static void config_can_##inst##_irq(void) \
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{ \
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LOG_DBG("Enable CAN##inst## IRQ"); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_0, irq), \
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DT_INST_IRQ_BY_NAME(inst, line_0, priority), can_mcan_line_0_isr, \
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DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(inst, line_0, irq)); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_1, irq), \
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DT_INST_IRQ_BY_NAME(inst, line_1, priority), can_mcan_line_1_isr, \
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DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(inst, line_1, irq)); \
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}
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#define CAN_SAM_CFG_INST(inst) \
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CAN_MCAN_DT_INST_CALLBACKS_DEFINE(inst, can_sam_cbs_##inst); \
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CAN_MCAN_DT_INST_MRAM_DEFINE(inst, can_sam_mram_##inst); \
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\
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static const struct can_sam_config can_sam_cfg_##inst = { \
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.base = CAN_MCAN_DT_INST_MCAN_ADDR(inst), \
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.mram = (mem_addr_t)POINTER_TO_UINT(&can_sam_mram_##inst), \
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.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(inst), \
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.divider = DT_INST_PROP(inst, divider), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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.config_irq = config_can_##inst##_irq, \
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}; \
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\
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static const struct can_mcan_config can_mcan_cfg_##inst = \
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CAN_MCAN_DT_CONFIG_INST_GET(inst, &can_sam_cfg_##inst, \
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&can_sam_ops, \
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&can_sam_cbs_##inst);
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#define CAN_SAM_DATA_INST(inst) \
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static struct can_mcan_data can_mcan_data_##inst = \
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CAN_MCAN_DATA_INITIALIZER(NULL);
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#define CAN_SAM_DEVICE_INST(inst) \
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DEVICE_DT_INST_DEFINE(inst, &can_sam_init, NULL, \
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&can_mcan_data_##inst, \
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&can_mcan_cfg_##inst, \
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POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
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&can_sam_driver_api);
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#define CAN_SAM_INST(inst) \
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CAN_MCAN_DT_INST_BUILD_ASSERT_MRAM_CFG(inst); \
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PINCTRL_DT_INST_DEFINE(inst); \
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CAN_SAM_IRQ_CFG_FUNCTION(inst) \
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CAN_SAM_CFG_INST(inst) \
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CAN_SAM_DATA_INST(inst) \
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CAN_SAM_DEVICE_INST(inst)
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DT_INST_FOREACH_STATUS_OKAY(CAN_SAM_INST)
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