Dominik Kilian cbaafe209c boards: nordic: ipc: added dcache alignement ... The nRF54 and nRF92 chips has data cache, which means the ICMsg and ICBMsg must be configured to follow required cache alignment of the shared memory. The `dcache-alignement` needs to be defined for that. Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>		2024-10-24 03:45:35 +01:00
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ipc_service	boards: nordic: ipc: added dcache alignement	2024-10-24 03:45:35 +01:00
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