Krzysztof Chruściński 923d313a04 dts: common: nordic: nrf54l: Add hfpll clock source ... Add 128 MHz clock source and use it for uart00. Baudrate setting must be adjusted based on uart clock source so without this change there is wrong baudrate on uart00. Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>		2024-11-29 11:44:49 +01:00
..
arc/synopsys	drivers: spi: dw: define max-xfer-size	2024-01-20 13:11:42 +01:00
arm	dts: arm: rakwireless: add RAK3172 LoRaWAN module	2024-11-28 20:52:54 +01:00
arm64	dma: dma_nxp_edma: drop the hal-cfg-index property	2024-11-16 15:07:45 -05:00
bindings	soc/mediatek/adsp: Source timer rate from DTS	2024-11-28 20:51:50 +01:00
common	dts: common: nordic: nrf54l: Add hfpll clock source	2024-11-29 11:44:49 +01:00
nios2/intel	dts: nios2: intel: Fix unit and first address mismatch	2024-09-18 15:30:24 +02:00
posix
riscv	arch: riscv64: smp: get msip base address from dts	2024-11-27 06:58:57 -05:00
sparc/gaisler	soc/gr716a: Enable GPIO support on LEON GR716A	2024-07-29 14:27:15 +02:00
x86/intel	dts/x86: use proper unit-address values	2024-11-18 13:18:53 -05:00
xtensa	dtsi: espressif: add missing address-cell entries	2024-11-27 10:38:44 -05:00
binding-template.yaml
Kconfig	dts: drop HAS_DTS	2023-10-20 12:18:17 -07:00