Francois Ramu a103d63b8f include: binding defines division factor for stm32 MCO prescaler ... Depending on the stm32 serie the MCO1/2 prescaler is a value set in the CFGR register to divide the MCO output clock. Use the same model based on the RefMan for other stm32 series than stm32C0/F4/F7/H5/H7, once the MCO is in the DTS. Signed-off-by: Francois Ramu <francois.ramu@st.com>		2024-12-05 19:59:47 -05:00
..
arc/synopsys	drivers: spi: dw: define max-xfer-size	2024-01-20 13:11:42 +01:00
arm	dts: arm: stm32f411 compatible for PLL I2S	2024-12-05 19:59:47 -05:00
arm64	dts: bindings: rename nxp,imx-lpi2c compatible	2024-12-04 14:15:52 -05:00
bindings	include: binding defines division factor for stm32 MCO prescaler	2024-12-05 19:59:47 -05:00
common	dts: common: nordic: Add clock property for fast PWM120	2024-12-02 14:25:09 +01:00
nios2/intel	dts: nios2: intel: Fix unit and first address mismatch	2024-09-18 15:30:24 +02:00
posix
riscv	drivers: mfd: it8801_altctrl: Add alternate controller for MFD	2024-12-03 19:56:50 +01:00
sparc/gaisler	soc/gr716a: Enable GPIO support on LEON GR716A	2024-07-29 14:27:15 +02:00
x86/intel	dts/x86: use proper unit-address values	2024-11-18 13:18:53 -05:00
xtensa	dtsi: espressif: add missing address-cell entries	2024-11-27 10:38:44 -05:00
binding-template.yaml
Kconfig