a5fd0d184a
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
152 lines
4.6 KiB
C
152 lines
4.6 KiB
C
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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* Copyright (c) 2020-2022 Synopsys.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARCv2 Interrupt Unit device driver
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*
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* The ARCv2 interrupt unit has 16 allocated exceptions associated with
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* vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
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* The interrupt unit is optional in the ARCv2-based processors. When
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* building a processor, you can configure the processor to include an
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* interrupt unit. The ARCv2 interrupt unit is highly programmable.
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#ifdef CONFIG_ARC_CONNECT
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static void arc_shared_intc_init(void)
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{
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/*
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* Initialize all IDU interrupts:
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* - select round-robbin
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* - disable all lines
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*/
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BUILD_ASSERT(CONFIG_NUM_IRQS > ARC_CONNECT_IDU_IRQ_START);
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__ASSERT(z_arc_v2_core_id() == ARC_MP_PRIMARY_CPU_ID,
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"idu interrupts must be inited from primary core");
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z_arc_connect_idu_disable();
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for (uint32_t i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) {
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/*
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* TODO: don't use z_arc_connect_idu* functions to avoid
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* locking/unlocking every time.
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*/
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/* Disable (mask) line */
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z_arc_connect_idu_set_mask(i, 0x1);
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z_arc_connect_idu_set_mode(i, ARC_CONNECT_INTRPT_TRIGGER_LEVEL,
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ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN);
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/*
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* Fake round-robin: we allow to distribute interrupts only to primary core as
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* secondary cores may be not initialized yet.
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*/
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z_arc_connect_idu_set_dest(i, BIT(ARC_MP_PRIMARY_CPU_ID));
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}
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z_arc_connect_idu_enable();
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}
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/* Allow to schedule IRQ to all cores after we bring up all secondary cores */
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static int arc_shared_intc_update_post_smp(void)
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{
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__ASSERT(z_arc_v2_core_id() == ARC_MP_PRIMARY_CPU_ID,
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"idu interrupts must be updated from primary core");
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z_arc_connect_idu_disable();
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for (uint32_t i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) {
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/* TODO: take arc_connect_spinlock one time to avoid locking/unlocking every time */
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z_arc_connect_idu_set_dest(i, BIT_MASK(arch_num_cpus()));
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}
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z_arc_connect_idu_enable();
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return 0;
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}
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SYS_INIT(arc_shared_intc_update_post_smp, SMP, 0);
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#endif /* CONFIG_ARC_CONNECT */
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/* lowest IRQ priority */
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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#define ARC_IRQ_DEFAULT_PRIORITY ((CONFIG_NUM_IRQ_PRIO_LEVELS - 1) | _ARC_V2_IRQ_PRIORITY_SECURE)
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#else
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#define ARC_IRQ_DEFAULT_PRIORITY (CONFIG_NUM_IRQ_PRIO_LEVELS - 1)
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#endif
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static inline void arc_core_intc_init_nolock(uint32_t irq, uint32_t state)
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{
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z_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
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z_arc_v2_aux_reg_write(_ARC_V2_IRQ_PRIORITY, ARC_IRQ_DEFAULT_PRIORITY);
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z_arc_v2_aux_reg_write(_ARC_V2_IRQ_TRIGGER, _ARC_V2_INT_LEVEL);
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z_arc_v2_aux_reg_write(_ARC_V2_IRQ_ENABLE, state);
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}
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/*
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* Initialize the core private interrupt controller.
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*
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* This function must be called on each CPU in case of SMP system.
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*
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* NOTE: core interrupts are still globally disabled at this point (STATUS32.IE = 0), so there is
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* no need to protect the window between a write to IRQ_SELECT and subsequent writes to the
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* selected IRQ's registers with locks.
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*/
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void arc_core_private_intc_init(void)
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{
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/*
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* Interrupts from 0 to 15 are exceptions and they are ignored by IRQ auxiliary registers.
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* We skip those interrupt lines while setting up core private interrupt controller.
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*/
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BUILD_ASSERT(CONFIG_GEN_IRQ_START_VECTOR == 16);
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/*
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* System with IDU case (most likely multi-core system):
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* - disable private IRQs: they will be enabled with irq_enable before usage
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* - enable shared (IDU) IRQs: their enabling / disabling is controlled via IDU, so we
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* always pass them via core private interrupt controller.
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* System without IDU case (single-core system):
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* - disable all IRQs: they will be enabled with irq_enable before usage
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*/
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#ifdef CONFIG_ARC_CONNECT
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for (uint32_t irq = CONFIG_GEN_IRQ_START_VECTOR; irq < ARC_CONNECT_IDU_IRQ_START; irq++) {
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arc_core_intc_init_nolock(irq, _ARC_V2_INT_DISABLE);
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}
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for (uint32_t irq = ARC_CONNECT_IDU_IRQ_START; irq < CONFIG_NUM_IRQS; irq++) {
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arc_core_intc_init_nolock(irq, _ARC_V2_INT_ENABLE);
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}
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#else
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for (uint32_t irq = CONFIG_GEN_IRQ_START_VECTOR; irq < CONFIG_NUM_IRQS; irq++) {
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arc_core_intc_init_nolock(irq, _ARC_V2_INT_DISABLE);
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}
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#endif /* CONFIG_ARC_CONNECT */
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}
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static int arc_irq_init(void)
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{
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#ifdef CONFIG_ARC_CONNECT
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arc_shared_intc_init();
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#endif /* CONFIG_ARC_CONNECT */
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/*
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* We initialize per-core part for core 0 here,
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* for rest cores it will be initialized in slave_start.
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*/
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arc_core_private_intc_init();
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return 0;
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}
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SYS_INIT(arc_irq_init, PRE_KERNEL_1, 0);
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