a9183cd518
The STM32L4x SoCs embeds a slightly different embedded flash controller from the STM32F4x SoCs. This particular controller has the following properties : - Up to 2 512KiB banks divided in 2KiB pages - Flash can be accessed in any sizes - Flash must be written in 64bit aligned 64bit double-words The drivers/flash/flash_stm32f4x.c is refactored into a new common drivers/flash/flash_stm32.c and drivers/flash/flash_stm32l4x.c is created with the STM32L4x specific functions. To ease the refactoring and keep common functions, the STM32L4x flash headers are slightly modified to match the hardware reference naming and solve compilation issues. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
152 lines
3.2 KiB
C
152 lines
3.2 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2017 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <string.h>
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#include <flash.h>
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#include <init.h>
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#include <soc.h>
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#include <flash_stm32.h>
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#define STM32L4X_BANK_SIZE_MAX 512
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#define STM32L4X_PAGE_SHIFT 11
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#define STM32L4X_FLASH_END \
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((u32_t)(STM32L4X_BANK_SIZE_MAX << STM32L4X_PAGE_SHIFT) - 1)
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/* offset and len must be aligned on 8, positive and not beyond end of flash */
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bool flash_stm32_valid_range(off_t offset, u32_t len)
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{
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return offset % 8 == 0 &&
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len % 8 == 0 &&
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offset >= 0 &&
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(offset + len - 1 <= STM32L4X_FLASH_END);
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}
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/* STM32L4xx devices can have up to 512 2K pages on two 256x2K pages banks */
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static unsigned int get_page(off_t offset)
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{
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return offset >> STM32L4X_PAGE_SHIFT;
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}
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static int write_dword(off_t offset, u64_t val, struct flash_stm32_priv *p)
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{
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volatile u32_t *flash = (u32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
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struct stm32l4x_flash *regs = p->regs;
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u32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->cr & FLASH_CR_LOCK) {
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return -EIO;
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}
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/* Check that no Flash main memory operation is ongoing */
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rc = flash_stm32_wait_flash_idle(p);
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if (rc < 0) {
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return rc;
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}
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/* Check if this double word is erased */
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if (flash[0] != 0xFFFFFFFFUL ||
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flash[1] != 0xFFFFFFFFUL) {
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return -EIO;
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}
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/* Set the PG bit */
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regs->cr |= FLASH_CR_PG;
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/* Flush the register write */
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tmp = regs->cr;
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/* Perform the data write operation at the desired memory address */
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flash[0] = (uint32_t)val;
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flash[1] = (uint32_t)(val >> 32);
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/* Wait until the BSY bit is cleared */
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rc = flash_stm32_wait_flash_idle(p);
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/* Clear the PG bit */
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regs->cr &= (~FLASH_CR_PG);
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return rc;
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}
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static int erase_page(unsigned int page, struct flash_stm32_priv *p)
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{
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struct stm32l4x_flash *regs = p->regs;
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u32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->cr & FLASH_CR_LOCK) {
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return -EIO;
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}
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/* Check that no Flash memory operation is ongoing */
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rc = flash_stm32_wait_flash_idle(p);
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if (rc < 0) {
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return rc;
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}
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/* Set the PER bit and select the page you wish to erase */
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regs->cr |= FLASH_CR_PER;
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#ifdef FLASH_CR_BKER
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regs->cr &= ~FLASH_CR_BKER_Msk;
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/* Select bank, only for DUALBANK devices */
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if (page >= 256)
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regs->cr |= FLASH_CR_BKER;
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#endif
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regs->cr &= ~FLASH_CR_PNB_Msk;
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regs->cr |= ((page % 256) << 3);
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/* Set the STRT bit */
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regs->cr |= FLASH_CR_STRT;
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/* flush the register write */
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tmp = regs->cr;
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/* Wait for the BSY bit */
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rc = flash_stm32_wait_flash_idle(p);
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regs->cr &= ~FLASH_CR_PER;
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return rc;
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}
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int flash_stm32_block_erase_loop(unsigned int offset, unsigned int len,
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struct flash_stm32_priv *p)
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{
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int i, rc = 0;
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i = get_page(offset);
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for (; i <= get_page(offset + len - 1) ; ++i) {
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rc = erase_page(i, p);
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if (rc < 0) {
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break;
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}
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}
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return rc;
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}
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int flash_stm32_write_range(unsigned int offset, const void *data,
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unsigned int len, struct flash_stm32_priv *p)
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{
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int i, rc = 0;
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for (i = 0; i < len; i += 8, offset += 8) {
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rc = write_dword(offset, ((const u64_t *) data)[i], p);
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if (rc < 0) {
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return rc;
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}
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}
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return rc;
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}
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