6edb0624d8
The exception mask needs to cover MCAUSE bits 11:0, there's no need to overengineer this setting using DT properties. Ref. https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html#mcause Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> |
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| gd32vf103.dtsi | ||
| gd32vf103X8.dtsi | ||
| gd32vf103Xb.dtsi | ||