8b39d4a613
Xtensa cache line sizes aren't an obtuse area of pedantry like they are in x86. Different cores already in Zephyr are already using variant cache line sizes (64 and 128 bytes are both common). And I tripped over this by using the wrong value because the kconfig was being inherited (incorrectly) from a default somewhere. Xtensa exposes the correct value in core-isa.h (well, unless the toolchain/hal gets messed up). Add a check to make sure that our platform kconfig gets it right. Note that qemu/dc233c was already getting this wrong, leaving the value at the kconfig default of zero. That was benign (qemu doesn't provide any cache emulation for incoherent DMA), but needs to be fixed. Signed-off-by: Andy Ross <andyross@google.com> |
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| arc | ||
| arm | ||
| arm64 | ||
| common | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| archs.yml | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.v1 | ||
| Kconfig.v2 | ||