Yong Cong Sin e0ce096b91 tests: benchmarks/sched: limit CPU to 1 for Intel ADSP ACE ... Due to addition of busy threads running on other cores, and the simulator runs in single thread bouncing through all cores, we are wasting quite a bit of time just busy waiting. This makes each simulator run too long for CI. So limit CPU number to 1. Signed-off-by: Daniel Leung <daniel.leung@intel.com> Signed-off-by: Yong Cong Sin <ycsin@meta.com>		2024-11-16 14:07:08 -05:00
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app_kernel	build: namespace the generated headers with zephyr/	2024-05-28 22:03:55 +02:00
cmsis_dsp	boards: mps3: Add support for corstone300/an552	2024-10-26 03:58:05 +01:00
data_structure_perf	tests/*: Switch integration platform to native_sim	2023-11-30 09:42:25 -05:00
footprints	build: namespace the generated headers with zephyr/	2024-05-28 22:03:55 +02:00
latency_measure	tests: Add objcore to latency_measure testcase.yaml	2024-11-07 18:42:03 -08:00
mbedtls	modules: mbedtls: rename CONFIG_MBEDTLS_MAC_*_ENABLED and rm duplicates	2024-05-29 08:39:26 +02:00
sched	tests: benchmarks/sched: limit CPU to 1 for Intel ADSP ACE	2024-11-16 14:07:08 -05:00
sched_queues	tests: scheduler queue benchmarks	2024-10-07 20:16:20 -04:00
sched_userspace	userspace tests/samples: Exclude in posix arch	2023-10-24 09:05:29 +02:00
sys_kernel	tests: Update sys_kernel benchmark	2023-10-17 21:48:51 +03:00
wait_queues	tests: benchmarks: wait_queues: Increase test timeout to 120s	2024-10-22 19:04:37 -04:00