e297293a54
The MAX22017 DAC provides two 16 Channel Analog outputs and 6 GPIOs. Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
390 lines
9.5 KiB
C
390 lines
9.5 KiB
C
/*
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* Copyright (c) 2024 Analog Devices Inc.
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* Copyright (c) 2024 Baylibre SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT adi_max22017
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/irq.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/sys/crc.h>
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LOG_MODULE_REGISTER(mfd_max22017, CONFIG_MFD_LOG_LEVEL);
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#include <zephyr/drivers/mfd/max22017.h>
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struct max22017_config {
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struct spi_dt_spec spi;
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const struct gpio_dt_spec gpio_reset;
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const struct gpio_dt_spec gpio_int;
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bool crc_mode;
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};
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int max22017_reg_read(const struct device *dev, uint8_t addr, uint16_t *value)
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{
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int ret;
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const struct max22017_config *config = dev->config;
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const struct max22017_data *data = dev->data;
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uint8_t rxbuffer[4] = {0};
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size_t recv_len = 3;
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*value = 0;
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addr = FIELD_PREP(MAX22017_SPI_TRANS_ADDR, addr) | FIELD_PREP(MAX22017_SPI_TRANS_DIR, 1);
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if (data->crc_enabled) {
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recv_len += 1;
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}
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const struct spi_buf txb[] = {
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{
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.buf = &addr,
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.len = 1,
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},
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};
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const struct spi_buf rxb[] = {
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{
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.buf = rxbuffer,
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.len = recv_len,
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},
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};
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struct spi_buf_set tx = {
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.buffers = txb,
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.count = ARRAY_SIZE(txb),
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};
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struct spi_buf_set rx = {
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.buffers = rxb,
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.count = ARRAY_SIZE(rxb),
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};
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ret = spi_transceive_dt(&config->spi, &tx, &rx);
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if (ret) {
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return ret;
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}
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if (!data->crc_enabled) {
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goto out_skip_crc;
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}
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uint8_t crc_in[] = {addr, rxbuffer[1], rxbuffer[2]};
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ret = crc8(crc_in, 3, MAX22017_CRC_POLY, 0, true);
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if (ret != rxbuffer[3]) {
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LOG_ERR("Reg read: CRC Mismatch calculated / read: %x / %x", ret, rxbuffer[3]);
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return -EINVAL;
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}
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out_skip_crc:
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*value = rxbuffer[1] | rxbuffer[2] << 8;
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*value = sys_be16_to_cpu(*value);
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return 0;
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}
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int max22017_reg_write(const struct device *dev, uint8_t addr, uint16_t value)
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{
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uint8_t crc;
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size_t crc_len = 0;
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const struct max22017_config *config = dev->config;
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const struct max22017_data *data = dev->data;
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addr = FIELD_PREP(MAX22017_SPI_TRANS_ADDR, addr) | FIELD_PREP(MAX22017_SPI_TRANS_DIR, 0);
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value = sys_cpu_to_be16(value);
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if (data->crc_enabled) {
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uint8_t crc_in[] = {addr, ((uint8_t *)&value)[0], ((uint8_t *)&value)[1]};
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crc_len = 1;
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crc = crc8(crc_in, 3, MAX22017_CRC_POLY, 0, true);
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}
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const struct spi_buf buf[] = {
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{
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.buf = &addr,
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.len = 1,
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},
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{
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.buf = &value,
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.len = 2,
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},
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{
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.buf = &crc,
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.len = crc_len,
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},
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};
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struct spi_buf_set tx = {
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.buffers = buf,
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.count = ARRAY_SIZE(buf),
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};
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return spi_write_dt(&config->spi, &tx);
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}
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static int max22017_reset(const struct device *dev)
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{
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int ret = 0;
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uint16_t ao_sta;
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const struct max22017_config *config = dev->config;
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if (config->gpio_reset.port != NULL) {
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ret = gpio_pin_set_dt(&config->gpio_reset, 0);
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if (ret) {
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return ret;
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}
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k_sleep(K_MSEC(100));
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ret = gpio_pin_set_dt(&config->gpio_reset, 1);
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k_sleep(K_MSEC(500));
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} else {
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ret = max22017_reg_write(dev, MAX22017_GEN_RST_CTRL_OFF,
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FIELD_PREP(MAX22017_GEN_RST_CTRL_GEN_RST, 1));
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if (ret) {
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return ret;
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}
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k_sleep(K_MSEC(100));
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ret = max22017_reg_write(dev, MAX22017_GEN_RST_CTRL_OFF,
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FIELD_PREP(MAX22017_GEN_RST_CTRL_GEN_RST, 0));
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if (ret) {
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return ret;
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}
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k_sleep(K_MSEC(500));
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ret = max22017_reg_read(dev, MAX22017_AO_STA_OFF, &ao_sta);
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if (ret) {
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return ret;
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}
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if (FIELD_GET(MAX22017_AO_STA_BUSY_STA, ao_sta)) {
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ret = -EBUSY;
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}
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}
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return ret;
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}
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static void max22017_isr(const struct device *dev, struct gpio_callback *gpio_cb, uint32_t pins)
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{
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struct max22017_data *data = CONTAINER_OF(gpio_cb, struct max22017_data, callback_int);
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int ret;
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k_mutex_lock(&data->lock, K_FOREVER);
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ret = k_work_submit(&data->int_work);
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if (ret < 0) {
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LOG_WRN("Could not submit int work: %d", ret);
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}
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k_mutex_unlock(&data->lock);
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}
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static void max22017_int_worker(struct k_work *work)
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{
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struct max22017_data *data = CONTAINER_OF(work, struct max22017_data, int_work);
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const struct device *dev = data->dev;
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int ret;
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uint16_t gen_int;
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k_mutex_lock(&data->lock, K_FOREVER);
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ret = max22017_reg_read(dev, MAX22017_GEN_INT_OFF, &gen_int);
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if (ret) {
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LOG_ERR("Unable to read GEN_INT register");
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goto fail;
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}
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if (FIELD_GET(MAX22017_GEN_INT_FAIL_INT, gen_int)) {
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LOG_ERR("Boot failure");
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}
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ret = FIELD_GET(MAX22017_GEN_INT_CONV_OVF_INT, gen_int);
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if (ret) {
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LOG_ERR("Conversion failure on channels: %s %s", (ret & BIT(0)) ? "0" : "",
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(ret & BIT(1)) ? "1" : "");
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}
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ret = FIELD_GET(MAX22017_GEN_INT_OPENWIRE_DTCT_INT, gen_int);
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if (ret) {
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LOG_ERR("Openwire detected on channels: %s %s", (ret & BIT(0)) ? "0" : "",
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(ret & BIT(1)) ? "1" : "");
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}
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if (FIELD_GET(MAX22017_GEN_INT_HVDD_INT, gen_int)) {
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LOG_ERR("HVDD/HVSS voltage difference below 1.5V");
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}
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if (FIELD_GET(MAX22017_GEN_INT_TMOUT_INT, gen_int)) {
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LOG_ERR("SPI transaction timeout");
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}
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ret = FIELD_GET(MAX22017_GEN_INT_THSHDN_INT, gen_int);
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if (ret) {
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LOG_ERR("Thermal shutdown AO channels: %s %s", (ret & BIT(0)) ? "0" : "",
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(ret & BIT(1)) ? "1" : "");
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}
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ret = FIELD_GET(MAX22017_GEN_INT_THWRNG_INT, gen_int);
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if (ret) {
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LOG_ERR("Thermal warning AO channels: %s %s", (ret & BIT(0)) ? "0" : "",
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(ret & BIT(1)) ? "1" : "");
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}
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ret = FIELD_GET(MAX22017_GEN_INT_OVC_INT, gen_int);
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if (ret) {
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LOG_ERR("Over current on channels: %s %s", (ret & BIT(0)) ? "0" : "",
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(ret & BIT(1)) ? "1" : "");
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}
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if (FIELD_GET(MAX22017_GEN_INT_CRC_INT, gen_int)) {
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LOG_ERR("CRC Error");
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}
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ret = FIELD_GET(MAX22017_GEN_INT_GPI_INT, gen_int);
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if (ret) {
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LOG_INF("GPI Interrupt: %d", ret);
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#ifdef CONFIG_GPIO_MAX22017
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uint16_t gpi_sta, lsb;
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ret = max22017_reg_read(dev, MAX22017_GEN_GPI_INT_STA_OFF, &gpi_sta);
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if (ret) {
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goto fail;
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}
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/* Aggregate both positive and negative edge together */
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gpi_sta = FIELD_GET(MAX22017_GEN_GPI_INT_GPI_NEG_EDGE_INT, gpi_sta) |
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FIELD_GET(MAX22017_GEN_GPI_INT_GPI_POS_EDGE_INT, gpi_sta);
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while (gpi_sta) {
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lsb = LSB_GET(gpi_sta);
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gpio_fire_callbacks(&data->callbacks_gpi, dev, lsb);
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gpi_sta &= ~lsb;
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}
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#endif
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}
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fail:
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k_mutex_unlock(&data->lock);
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}
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static int max22017_init(const struct device *dev)
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{
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const struct max22017_config *config = dev->config;
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struct max22017_data *data = dev->data;
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uint16_t version;
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int ret;
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uint16_t gen_cnfg = 0, gen_int_en = 0;
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if (!spi_is_ready_dt(&config->spi)) {
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LOG_ERR("SPI spi %s not ready", config->spi.bus->name);
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return -ENODEV;
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}
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if (config->gpio_reset.port != NULL) {
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ret = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
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if (ret) {
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LOG_ERR("failed to initialize GPIO reset pin");
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return ret;
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}
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}
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ret = max22017_reset(dev);
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if (ret) {
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LOG_ERR("failed to reset MAX22017");
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return ret;
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}
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data->dev = dev;
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k_work_init(&data->int_work, max22017_int_worker);
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k_mutex_init(&data->lock);
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if (config->gpio_int.port) {
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ret = gpio_pin_configure_dt(&config->gpio_int, GPIO_INPUT);
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if (ret) {
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LOG_ERR("failed to initialize GPIO interrupt pin");
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goto fail;
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}
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ret = gpio_pin_interrupt_configure_dt(&config->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
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if (ret) {
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LOG_ERR("failed to configure interrupt pin");
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goto fail;
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}
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gpio_init_callback(&data->callback_int, max22017_isr, BIT(config->gpio_int.pin));
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ret = gpio_add_callback(config->gpio_int.port, &data->callback_int);
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if (ret) {
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LOG_ERR("failed to add data ready callback");
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goto fail;
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}
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}
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k_mutex_lock(&data->lock, K_FOREVER);
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ret = max22017_reg_write(dev, MAX22017_AO_CNFG_OFF, 0);
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if (ret) {
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return ret;
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}
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ret = max22017_reg_write(dev, MAX22017_AO_DATA_CHn_OFF(0), 0);
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if (ret) {
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goto fail;
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}
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ret = max22017_reg_write(dev, MAX22017_AO_DATA_CHn_OFF(1), 0);
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if (ret) {
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goto fail;
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}
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if (config->crc_mode) {
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gen_cnfg |= FIELD_PREP(MAX22017_GEN_CNFG_CRC_EN, 1);
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gen_int_en |= FIELD_PREP(MAX22017_GEN_INTEN_CRC_INTEN, 1);
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}
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ret = max22017_reg_write(dev, MAX22017_GEN_INTEN_OFF, gen_int_en);
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if (ret) {
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goto fail;
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}
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ret = max22017_reg_write(dev, MAX22017_GEN_CNFG_OFF, gen_cnfg);
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if (ret) {
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goto fail;
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}
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if (config->crc_mode) {
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data->crc_enabled = true;
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}
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ret = max22017_reg_read(dev, MAX22017_GEN_ID_OFF, &version);
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if (ret) {
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LOG_ERR("Unable to read MAX22017 version over SPI: %d", ret);
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goto fail;
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}
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LOG_INF("MAX22017 version: 0x%lx 0x%lx", FIELD_GET(MAX22017_GEN_ID_PROD_ID, version),
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FIELD_GET(MAX22017_GEN_ID_REV_ID, version));
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fail:
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k_mutex_unlock(&data->lock);
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return ret;
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}
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#define INST_DT_MAX22017(index) \
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static const struct max22017_config max22017_config_##index = { \
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.spi = SPI_DT_SPEC_INST_GET(index, SPI_OP_MODE_MASTER | SPI_WORD_SET(8U), 0U), \
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.gpio_int = GPIO_DT_SPEC_INST_GET_OR(index, int_gpios, {0}), \
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.gpio_reset = GPIO_DT_SPEC_INST_GET_OR(index, rst_gpios, {0}), \
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.crc_mode = DT_INST_PROP_OR(index, crc_mode, 0), \
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}; \
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\
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static struct max22017_data max22017_data_##index; \
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\
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DEVICE_DT_INST_DEFINE(index, max22017_init, NULL, &max22017_data_##index, \
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&max22017_config_##index, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(INST_DT_MAX22017);
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