e6dd68ec89
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be enabled, instead of relying of dependencies. To do that, introduce a new `CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected by SoC when it implemented global pointer (GP) initialization for relative addressing in its linker. `CONFIG_RISCV_GP` will be the default choice when `CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y` Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
31 lines
685 B
Text
31 lines
685 B
Text
# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
|
|
# Copyright (c) 2024 Antmicro <www.antmicro.com>
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
config SOC_SERIES_SIFIVE_FREEDOM_FU500
|
|
bool
|
|
|
|
select 64BIT
|
|
|
|
# RISC-V options
|
|
select RISCV
|
|
select RISCV_PRIVILEGED
|
|
select RISCV_HAS_PLIC
|
|
select RISCV_PMP
|
|
select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
|
|
|
|
select RISCV_ISA_RV64I
|
|
select RISCV_ISA_EXT_M
|
|
select RISCV_ISA_EXT_A
|
|
select RISCV_ISA_EXT_C
|
|
select RISCV_ISA_EXT_ZICSR
|
|
select RISCV_ISA_EXT_ZIFENCEI
|
|
|
|
select SOC_EARLY_INIT_HOOK
|
|
select INCLUDE_RESET_VECTOR
|
|
imply XIP
|
|
|
|
config SOC_SIFIVE_FREEDOM_FU540_U54
|
|
bool
|
|
select RISCV_ISA_EXT_G
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|