zephyr/soc/mediatek/mt8xxx
Andy Ross b4fb833eb9 soc/mediatek/adsp: Source timer rate from DTS
These devices have an architecturally fixed 13 MHz clock device.  But
thankfully you can put a default into a DTS binding so we don't have
to repeat it for all of them.

Signed-off-by: Andy Ross <andyross@google.com>
2024-11-28 20:51:50 +01:00
..
mt8186
mt8188
mt8195
mt8196 boards/mediatek: Add mt8196_adsp 2024-11-28 20:51:50 +01:00
CMakeLists.txt
cpuclk.c
gen_img.py soc/mediatek: Ruffify python scripts 2024-11-28 20:51:50 +01:00
irq.c boards/mediatek: Add mt8196_adsp 2024-11-28 20:51:50 +01:00
Kconfig
Kconfig.defconfig soc/mediatek/adsp: Source timer rate from DTS 2024-11-28 20:51:50 +01:00
Kconfig.soc boards/mediatek: Add mt8196_adsp 2024-11-28 20:51:50 +01:00
linker.ld
mbox.c
mtk_adsp_load.py soc/mediatek: Ruffify python scripts 2024-11-28 20:51:50 +01:00
soc.c boards/mediatek: Add mt8196_adsp 2024-11-28 20:51:50 +01:00
soc.h
soc.yml boards/mediatek: Add mt8196_adsp 2024-11-28 20:51:50 +01:00