f72ef5c237
Introduce new binding "st,stm32u5-otghs-phy" for OTG_HS PHY. This allows to configure clock source and handle STM32U5 specific OTG_HS PHY behavior in driver implementation in a more readable way. Move OTG_HS PHY clock selection (previously <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>) from OTG_HS node to OTG_HS PHY node. Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the stm32u5 CCIPR2 register (RM0456 Rev 5, Section 11.8.47). Support enabling OTG_HS PHY clock, which is bit 15 (OTGHSPHYEN) in RCC_AHB2ENR1. Change OTG_HS clock to be bit 14 (OTGEN). Calculate in runtime OTG_HS PHY clock source frequency. Try to match that to supported (16, 19.2, 20, 24, 26, 32 MHz) frequencies and select proper option with HAL_SYSCFG_SetOTGPHYReferenceClockSelection() API (instead of hardcoded 16 MHz selection). Co-authored-by: Adrian Chadd <adrian.chadd@meta.com> Signed-off-by: Adrian Chadd <adrian.chadd@meta.com> Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev> |
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| .. | ||
| arc/synopsys | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2/intel | ||
| posix | ||
| riscv | ||
| sparc/gaisler | ||
| x86/intel | ||
| xtensa | ||
| binding-template.yaml | ||
| Kconfig | ||