fb60aab245
In order to bring consistency in-tree, migrate all drivers to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to #45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
61 lines
1.3 KiB
C
61 lines
1.3 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#if STM32_SYSCLK_SRC_PLL
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/* Macros to fill up division factors values */
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#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
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#define pllm(v) z_pllm(v)
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#define z_pllp(v) LL_RCC_PLLP_DIV_ ## v
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#define pllp(v) z_pllp(v)
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/**
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* @brief Set up pll configuration
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*/
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int config_pll_sysclock(void)
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{
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uint32_t pll_source, pll_m, pll_n, pll_p;
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pll_n = STM32_PLL_N_MULTIPLIER;
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pll_m = pllm(STM32_PLL_M_DIVISOR);
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pll_p = pllp(STM32_PLL_P_DIVISOR);
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/* Configure PLL source */
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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pll_source = LL_RCC_PLLSOURCE_HSI;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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pll_source = LL_RCC_PLLSOURCE_HSE;
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} else {
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return -ENOTSUP;
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}
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LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_m, pll_n, pll_p);
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return 0;
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}
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#endif /* STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Power Interface clock enabled by default */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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}
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