fbd9dd4526
This adds support for the single-vector trapping (SVT) model, defined by SPARC-V8 Embedded (V8E) Architecture Specification. SVT is available in most LEON processors. With single-vector trapping enabled, all traps are vectored through a single trap vector (TBR.A) rather than one 16-byte entry for each trap type. This improves memory utilization because the full 4 KiB trap table is not needed. This implementation uses a two-level of lookup table to find the handler for the trap type (0..255). - Execution time is constant. - Condition flags are preserved. - The implementation footprint is 60 bytes .text and 284 bytes .rodata. For comparison, a non-SVT table is always 4096 .text. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com> |
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| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| common | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| archs.yml | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.v1 | ||
| Kconfig.v2 | ||