760210f39d
Separate the current driver for the FPGA iCE40 into two different ones. One implements only the SPI load mode, the other one only the GPIO bitbang mode. Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
84 lines
3.7 KiB
C
84 lines
3.7 KiB
C
/*
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* Copyright (c) 2022 Meta
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* Copyright (c) 2024 SILA Embedded Solutions GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SUBSYS_FPGA_FPGA_ICE40_COMMON_H_
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#define ZEPHYR_SUBSYS_FPGA_FPGA_ICE40_COMMON_H_
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#include <stdbool.h>
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#include <stdint.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/fpga.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/spi.h>
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/*
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* Values in Hz, intentionally to be comparable with the spi-max-frequency
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* property from DT bindings in spi-device.yaml.
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*/
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#define FPGA_ICE40_SPI_HZ_MIN 1000000
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#define FPGA_ICE40_SPI_HZ_MAX 25000000
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#define FPGA_ICE40_CRESET_DELAY_US_MIN 1 /* 200ns absolute minimum */
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#define FPGA_ICE40_CONFIG_DELAY_US_MIN 1200
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#define FPGA_ICE40_LEADING_CLOCKS_MIN 8
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#define FPGA_ICE40_TRAILING_CLOCKS_MIN 49
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#define FPGA_ICE40_CONFIG_DEFINE(inst, derived_config_) \
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BUILD_ASSERT(DT_INST_PROP(inst, spi_max_frequency) >= FPGA_ICE40_SPI_HZ_MIN); \
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BUILD_ASSERT(DT_INST_PROP(inst, spi_max_frequency) <= FPGA_ICE40_SPI_HZ_MAX); \
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BUILD_ASSERT(DT_INST_PROP(inst, config_delay_us) >= FPGA_ICE40_CONFIG_DELAY_US_MIN); \
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BUILD_ASSERT(DT_INST_PROP(inst, config_delay_us) <= UINT16_MAX); \
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BUILD_ASSERT(DT_INST_PROP(inst, creset_delay_us) >= FPGA_ICE40_CRESET_DELAY_US_MIN); \
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BUILD_ASSERT(DT_INST_PROP(inst, creset_delay_us) <= UINT16_MAX); \
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BUILD_ASSERT(DT_INST_PROP(inst, leading_clocks) >= FPGA_ICE40_LEADING_CLOCKS_MIN); \
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BUILD_ASSERT(DT_INST_PROP(inst, leading_clocks) <= UINT8_MAX); \
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BUILD_ASSERT(DT_INST_PROP(inst, trailing_clocks) >= FPGA_ICE40_TRAILING_CLOCKS_MIN); \
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BUILD_ASSERT(DT_INST_PROP(inst, trailing_clocks) <= UINT8_MAX); \
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\
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static const struct fpga_ice40_config fpga_ice40_config_##inst = { \
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.bus = SPI_DT_SPEC_INST_GET(inst, \
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SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA | \
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SPI_WORD_SET(8) | SPI_TRANSFER_MSB, \
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0), \
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.creset = GPIO_DT_SPEC_INST_GET(inst, creset_gpios), \
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.cdone = GPIO_DT_SPEC_INST_GET(inst, cdone_gpios), \
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.config_delay_us = DT_INST_PROP(inst, config_delay_us), \
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.creset_delay_us = DT_INST_PROP(inst, creset_delay_us), \
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.leading_clocks = DT_INST_PROP(inst, leading_clocks), \
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.trailing_clocks = DT_INST_PROP(inst, trailing_clocks), \
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.derived_config = derived_config_, \
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}
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struct fpga_ice40_data {
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uint32_t crc;
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/* simply use crc32 as info */
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char info[2 * sizeof(uint32_t) + 1];
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bool on;
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bool loaded;
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struct k_spinlock lock;
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};
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struct fpga_ice40_config {
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struct spi_dt_spec bus;
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struct gpio_dt_spec cdone;
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struct gpio_dt_spec creset;
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uint16_t creset_delay_us;
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uint16_t config_delay_us;
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uint8_t leading_clocks;
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uint8_t trailing_clocks;
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const void *derived_config;
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};
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void fpga_ice40_crc_to_str(uint32_t crc, char *s);
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enum FPGA_status fpga_ice40_get_status(const struct device *dev);
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int fpga_ice40_on(const struct device *dev);
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int fpga_ice40_off(const struct device *dev);
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int fpga_ice40_reset(const struct device *dev);
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const char *fpga_ice40_get_info(const struct device *dev);
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int fpga_ice40_init(const struct device *dev);
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#endif /* ZEPHYR_SUBSYS_FPGA_FPGA_ICE40_COMMON_H_ */
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